NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 529

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PDMA Interrupt Enable Control Register (PDMA_IERx)
Register
PDMA_IER0
PDMA_IER1
PDMA_IER2
PDMA_IER3
PDMA_IER4
PDMA_IER5
PDMA_IER6
PDMA_IER7
PDMA_IER8
Notice: Low Density only support PDMA channel 0.
Bits
[31:2]
[1]
[0]
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
Reserved
BLKD_IE
TABORT_IE
Offset
PDMA_BA_ch0+0x20
PDMA_BA_ch1+0x20
PDMA_BA_ch2+0x20
PDMA_BA_ch3+0x20
PDMA_BA_ch4+0x20
PDMA_BA_ch5+0x20
PDMA_BA_ch6+0x20
PDMA_BA_ch7+0x20
PDMA_BA_ch8+0x20
30
22
14
6
Reserved
PDMA Transfer Done Interrupt Enable
1 = Enable interrupt generator during PDMA transfer done.
0 = Disable interrupt generator during PDMA transfer done.
PDMA Read/Write Target Abort Interrupt Enable
1 = Enable target abort interrupt generation during PDMA transfer.
0 = Disable target abort interrupt generation during PDMA transfer.
29
21
13
5
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
PDMA Interrupt Enable Control Register CH0
PDMA Interrupt Enable Control Register CH1
PDMA Interrupt Enable Control Register CH2
PDMA Interrupt Enable Control Register CH3
PDMA Interrupt Enable Control Register CH4
PDMA Interrupt Enable Control Register CH5
PDMA Interrupt Enable Control Register CH6
PDMA Interrupt Enable Control Register CH7
PDMA Interrupt Enable Control Register CH8
28
20
12
4
- 529 -
Reserved
Reserved
Reserved
27
19
11
3
Publication Release Date: Oct 22, 2010
26
18
10
2
BLKD_IE
25
17
9
1
Revision V1.06
Reset Value
0x0000_0001
0x0000_0001
0x0000_0001
0x0000_0001
0x0000_0001
0x0000_0001
0x0000_0001
0x0000_0001
0x0000_0001
TABORT_IE
24
16
8
0