NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 544

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.19.4.3 EBI Operating Control
MCLK Control
In the chip, all EBI signals will be synchronized by MCLK when EBI is operating. When chip
connects to the external device with slower operating frequency, the MCLK can divide most to
HCLK/32 by setting MCLKDIV of register EBICON. Therefore, chip can suitable for a wide
frequency range of EBI device. If MCLK is set to HCLK/1, EBI signals are synchronized by
positive edge of MCLK, else by negative edge of MCLK.
Operation and Access Timing Control
In the start of access, chip select (nCS) asserts to low and wait one MCLK for address setup time
(tASU) for address stable. Then ALE asserts to high after address is stable and keeps for a period
of time (tALE) for address latch. After latch address, ALE asserts to low and wait one MCLK for
latch hold time (tLHD) and another one MCLK cycle (tA2D) that is inserted behind address hold
time to be the bus turn-around time for address change to data. Then nRD asserts to low when
read access or nWR asserts to low when write access. Then nRD or nWR asserts to high after
keeps access time (tACC) for reading output stable or writing finish. After that, EBI signals keep
for data access hold time (tAHD) and chip select asserts to high, address is released by current
access control.
EBI controller provides a flexible timing control for different external device. In EBI timing control,
tASU, tLHD and tA2D are fixed to 1 MCLK cycle, tAHD can modulate to 1~8 MCLK cycles by
setting ExttAHD of register EXTIME, tACC can modulate to 1~32 MCLK cycles by setting
ExttACC of register EXTIME, and tALE can modulate to 1~8 MCLK cycles by setting tALE of
register EBICON.
Parameter
tACC
tAHD
tASU
tLHD
tALE
tA2D
IDLE
NuMicro™ NUC100 Series Technical Reference Manual
0 ~ 15
1 ~ 32
Value
1 ~ 8
1 ~ 8
1
1
1
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
Unit
Description
Address Latch Setup Time.
ALE High Period. Controlled by ExttALE of EBICON.
Address Latch Hold Time.
Address To Data Delay (Bus Turn-Around Time).
Data Access Time. Controlled by ExttACC of EXTIME.
Data Access Hold Time. Controlled by ExttAHB of EXTIME.
Idle Cycle. Controlled by ExtIR2R and ExtIW2X of EXTIME.
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Publication Release Date: Dec. 22, 2010
Revision V1.06