AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 163
AT91SAM7SE256B-AUR
Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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22.5
22.5.1
22.6
22.6.1
22.6.1.1
6222F–ATARM–14-Jan-11
Product Dependencies
Functional Description
I/O Lines
External Memory Interface
External Memory Mapping
The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO
lines. The programmer must first program the PIO controller to assign the Static Memory Con-
troller pins to their peripheral function. If I/O lines of the Static Memory Controller are not used by
the application, they can be used for other purposes by the PIO Controller.
The memory map is defined by hardware and associates the internal 32-bit address space with
the external 23-bit address bus. Note that A[22:0] is only significant for 8-bit memory. A[22:1] is
used for 16-bit memory. If the physical memory device is smaller than the page size, it wraps
around and appears to be repeated within the page. The SMC correctly handles any valid
access to the memory device within the page. See
Figure 22-2. Case of an External Memory Smaller than Page Size
Memory
Map
1M Byte Device
1M Byte Device
1M Byte Device
1M Byte Device
SAM7SE512/256/32 Preliminary
Low
Low
Low
Low
Hi
Hi
Hi
Hi
Figure
22-2.
Base + 4M Bytes
Base + 3M Bytes
Base + 2M Bytes
Base + 1M Byte
Base
Repeat 3
Repeat 2
Repeat 1
163
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