AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 382
AT91SAM7SE256B-AUR
Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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32.10.6
Name:
Access:
Reset Value: 0x0000F009
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in
page 373
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
page 373
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in
382
31
23
15
–
–
7
–
SAM7SE512/256/32 Preliminary
and
and
TWI Status Register
TWI_SR
Read-only
Figure 32-30 on page
Figure 32-30 on page
OVRE
30
22
14
–
–
6
GACC
373.
373.
29
21
13
–
–
5
Figure 32-8 on page
Figure 32-10 on page
Figure 32-25 on page
SVACC
Figure 32-27 on page
Figure 32-8 on page 354
28
20
12
–
–
4
EOSACC
SVREAD
27
19
11
–
–
3
354.
355.
369,
371,
and in
Figure 32-28 on page
Figure 32-28 on page
SCLWS
TXRDY
26
18
10
Figure 32-10 on page
–
–
2
ARBLST
RXRDY
25
17
–
–
9
1
372,
372,
6222F–ATARM–14-Jan-11
355.
Figure 32-29 on
Figure 32-29 on
TXCOMP
NACK
24
16
–
–
8
0
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