AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 657
AT91SAM7SE256B-AUR
Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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43.2.7.5
43.2.8
43.2.8.1
43.2.9
43.2.9.1
43.2.9.2
43.2.9.3
6222F–ATARM–14-Jan-11
Two Wire Interface (TWI)
Universal Synchronous Asynchronous Receiver Transmitter (USART)
TWI: Switching from Slave to Master Mode
USART: Two Characters Sent with Hardware Handshaking
USART: DCD is Active High Instead of Low
SSC: First RK Clock Cycle when Rk Outputs a Clock During Data Transfer
USART: CTS in Hardware Handshaking
At the end of the data, the RK pin is set in high impedance which might be seen as an unex-
pected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used with the following conditions:
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
None.
When the TWI is set in slave mode and if a master write access is performed, the start event is
correctly generated but the SCL line is stuck at 1, so no transfer is possible.
Two software workarounds are possible:
When Hardware Handshaking is used and if CTS goes high near the end of the starting bit, a
character can be lost.
CTS must not go high during a time slot occurring between 2 Master Clock periods before the
starting bit and 16 Master Clock periods after the rising edge of the starting bit.
None.
When Hardware Handshaking is used and if CTS goes high during the TX of a character and if
the holding register (US_THR) is not empty, the content of the US_THR will also be transmitted.
Don’t use the PDC in transmit mode and do not fill US_THR before TXRDY is set at 1.
DCD signal is active at “High” level in USART block (Modem Mode).
DCD should be active at “Low” level.
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
1. Perform a software reset before going to master mode (TWI must be reconfigured).
2. Perform a slave read access before switching to master mode.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SAM7SE512/256/32 Preliminary
657
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