AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 88
AT91SAM7SE256B-AUR
Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
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18.3
18.3.1
18.3.2
88
Functional Description
SAM7SE512/256/32 Preliminary
Bus Arbiter
Address Decoder
The Memory Controller handles the internal ASB bus and arbitrates the accesses of both
masters.
It is made up of:
The MC handles only little-endian mode accesses. The masters work in little-endian mode only.
The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the
bus to one of the two masters. The Peripheral Data Controller has the highest priority; the ARM
processor has the lowest one.
The Memory Controller features an Address Decoder that first decodes the four highest bits of
the 32-bit address bus and defines 11 separate areas:
• A bus arbiter
• An address decoder
• An abort status
• A misalignment detector
• A memory protection unit
• An Embedded Flash Controller
• One 256-Mbyte address space for the internal memories
• Eight 256-Mbyte address spaces, each assigned to one of the eight chip select lines of the
• One 256-Mbyte address space reserved for the embedded peripherals
• An undefined address space of 1536M bytes that returns an Abort if accessed
External Bus Interface
6222F–ATARM–14-Jan-11
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