S9S08LG32J0VLF Freescale Semiconductor, S9S08LG32J0VLF Datasheet - Page 12

• Manufacturer Part Number: S9S08LG32J0VLF
• Description: IC MCU 8BIT 32KB FLASH 48LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08LG32J0VLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.9K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 9x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Processor Series: S08LG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 39
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08LG32
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical Characteristics
where:
For most applications, P
is:
Solving
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
for any value of T
2.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for automotive grade integrated circuits. During the
device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge
device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
12
Equation 1
T
θ
P
P
P
JA
A
D
int
I/O
ESD Protection and Latch-Up Immunity
= Ambient temperature, °C
= P
= Package thermal resistance, junction-to-ambient, °C/W
= I
= Power dissipation on input and output pins — user determined
A
Human Body
. Using this value of K, the values of P
int
Latch-up
DD
Model
Model
A
+ P
.
× V
and
I/O
DD
I/O
Equation 2
, Watts — chip internal power
<< P
Series resistance
Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
int
and can be neglected. An approximate relationship between P
for K gives:
Table 6. ESD and Latch-Up Test Conditions
K = P
Description
MC9S08LG32 Series Data Sheet, Rev. 7
D
P
× (T
D
= K ÷ (T
A
D
+ 273 °C) + θ
and T
J
J
+ 273 °C)
can be obtained by solving
Symbol
JA
R1
—
—
—
C
× (P
D
)
2
Value
Equation 1
1500
–2.5
100
7.5
3
D
and T
and
Freescale Semiconductor
J
Equation 2
(if P
Unit
D
pF
—
Ω
V
V
I/O
(at equilibrium)
is neglected)
iteratively
Eqn. 2
Eqn. 3