PK20N512VLK100 Freescale Semiconductor, PK20N512VLK100 Datasheet - Page 31

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PK20N512VLK100

Manufacturer Part Number
PK20N512VLK100
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheet

Specifications of PK20N512VLK100

Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
Peripherals
DMA, I²S, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 33x16b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PK20N512VLK100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Freescale Semiconductor, Inc.
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Num
Num
EP5
EP6
EP7
EP8
EP9
Operating voltage
Frequency of operation
Description
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
Table 22. EzPort switching specifications (continued)
K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 23. Flexbus switching specifications
EP3
EP5
Figure 9. EzPort Timing Diagram
Table continues on the next page...
EP6
EP4
EP7
Preliminary
EP8
EP9
Peripheral operating requirements and behaviors
Min.
EP2
2.7
Min.
2
5
0
Max.
3.6
50
Max.
12
12
Mhz
Unit
V
Unit
Notes
ns
ns
ns
ns
ns
31

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