PK40N512VLK100 Freescale Semiconductor, PK40N512VLK100 Datasheet
PK40N512VLK100
Specifications of PK40N512VLK100
Available stocks
Related parts for PK40N512VLK100
PK40N512VLK100 Summary of contents
Page 1
... Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © 2010–2011 Freescale Semiconductor, Inc. Preliminary Document Number: K40P81M100SF2 Rev. 4, 3/2011 K40P81M100SF2 • ...
Page 2
... I2S switching specifications................................51 6.9 Human-machine interfaces (HMI)......................................53 6.9.1 TSI electrical specifications................................53 6.9.2 LCD electrical characteristics.............................54 7 Dimensions...............................................................................55 7.1 Obtaining package dimensions.........................................55 8 Pinout........................................................................................56 8.1 K40 Signal Multiplexing and Pin Assignments..................56 8.2 K40 Pinouts.......................................................................59 9 Revision History........................................................................61 Preliminary Freescale Semiconductor, Inc. ...
Page 3
... Field Q Qualification status K## Kinetis family M Flash memory type K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. http://www.freescale.com Description • Fully qualified, general market flow • Prequalification • K40 • Program flash only • Program flash and FlexMemory Table continues on the next page ...
Page 4
... MC = 121 MAPBGA ( mm) • 144 LQFP ( mm) • 144 MAPBGA ( mm) • 196 MAPBGA ( mm) • 256 MAPBGA ( mm) • MHz • MHz • 100 = 100 MHz • 120 = 120 MHz • 150 = 150 MHz • Tape and reel • (Blank) = Trays Preliminary Values Freescale Semiconductor, Inc. ...
Page 5
... Example This is an example of an attribute: Symbol Description CIN_D Input capacitance: digital pins K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. Max. 0.9 1.1 Min. Max. 10 130 Min. ...
Page 6
... Result of exceeding a rating Measured characteristic K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 6 Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating Preliminary Max. Unit V Freescale Semiconductor, Inc. ...
Page 7
... Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Normal Limited operating operating range ...
Page 8
... Ambient temperature A V 3.3 V supply voltage DD 4 Ratings K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 8 Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Preliminary Max. Unit 130 µ 150 °C 105 °C 25 °C –40 °C Unit °C V Freescale Semiconductor, Inc. ...
Page 9
... Description V Digital supply voltage DD I Digital supply current DD V Digital input voltage (except RESET, EXTAL, and XTAL) DIO K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. –55 — — Min. — Min. -2000 -500 -100 Table continues on the next page... ...
Page 10
... V DD Table continues on the next page... Preliminary Min. Max. Unit –0 0 – – –0.3 3.63 V –0.3 3.63 V –0.3 6.0 V –0.3 3.8 V Max. Unit Notes 3.6 V 3.6 V 0.1 V 0.1 V 3.6 V — V — V 0.35 × 0.3 × — V Freescale Semiconductor, Inc. ...
Page 11
... V Bandgap voltage reference BG t Internal low power oscillator period LPO factory trimmed K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min 1.2 TBD , and induce an injection current when V SS supply LVD and POR operating requirements Min. ...
Page 12
... DD SS min and Vinput = and VLLSx→RUN recovery times in the following table Preliminary Typ. Max. Unit Notes 1.1 TBD V Max. Unit Notes — V — V — V — V 100 mA 0.5 V 0.5 V 0.5 V 0.5 V 100 mA 1 μ μA 50 kΩ kΩ 3 Freescale Semiconductor, Inc. ...
Page 13
... VLPS → RUN 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.1.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol Description I Analog supply current DDA K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. — DD — — — — — — ...
Page 14
... TBD — 35 TBD — 15 TBD — 0.4 TBD — 1.25 TBD — TBD TBD — 1.05 TBD — 50 TBD — 12 TBD — 8 TBD — 4 TBD — 2 TBD — 550 TBD Preliminary Unit Notes μA μA μA μA μ Freescale Semiconductor, Inc. ...
Page 15
... Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled The following data was measured under these conditions: • MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary General 15 ...
Page 16
... Radiated emissions voltage, band 4 RE4 V IEC and SAE level RE_IEC_SAE K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 16 Frequency Typ. band (MHz) 0.15–50 TBD 50–150 TBD 150–500 TBD 500–1000 TBD 0.15–1000 TBD Preliminary Unit Notes dBμ — Freescale Semiconductor, Inc. ...
Page 17
... Bus clock BUS f Flash clock FLASH f System and core clock SYS f Bus clock BUS K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc MHz SYS Table 8. Capacitance attributes Min. Normal run mode — 20 — — VLPR mode — — ...
Page 18
... Min. Max. — 1 Min. Max. 1.5 — 100 — 16 — TBD — 2 — — 12 — 36 — 32 — 36 Min. –40 –40 Preliminary Unit Notes MHz Unit Notes Bus clock 1 cycles Bus clock cycles Max. Unit 125 °C 105 °C Freescale Semiconductor, Inc. ...
Page 19
... Core modules 6.1.1 Debug trace timing specifications Table 10. Debug trace operating behaviors Symbol Description T Clock period cyc K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 81 MAPBGA TBD TBD TBD TBD TBD TBD ...
Page 20
... Serial Wire Debug J2 TCLK cycle period K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 Table continues on the next page... Preliminary Min. Max. Unit 2 — — ns — — — — Min. Max. Unit 2.7 3.6 V MHz 1/J1 — ns Freescale Semiconductor, Inc. ...
Page 21
... TCLK low to boundary scan output data valid J8 TCLK low to boundary scan output high-Z J9 TMS, TDI input data setup time to TCLK rise K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table continues on the next page... Preliminary Min. Max. ...
Page 22
... Figure 6. Boundary scan (JTAG) timing K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 Figure 5. Test clock input timing Preliminary Min. Max. Unit 1.4 — ns — 22.1 ns — 22.1 ns 100 — — Input data valid Output data valid Output data valid Freescale Semiconductor, Inc. ...
Page 23
... J13 TRST 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J11 J12 J11 Figure 7. Test Access Port timing J14 Figure 8 ...
Page 24
... TBD %f dco — 4 MHz — 5 MHz — µA TBD µs — — kHz — — kHz — 39.0625 kHz 25 MHz 2, 50 MHz 75 MHz 100 MHz Freescale Semiconductor, Inc ...
Page 25
... This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE crystal/resonator is being used as the reference, this specification assumes it is already running. K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — ...
Page 26
... Table continues on the next page... Preliminary Max. Unit Notes 3 — nA — μA — μA — μA — mA — — μA — μA — μA — mA — mA — mA — — — MΩ — MΩ — MΩ — MΩ Freescale Semiconductor, Inc. ...
Page 27
... Input clock frequency (external clock mode) ec_extal t Input clock duty cycle (external clock mode) dc_extal K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — — — — — ...
Page 28
... Min. Typ. 1.71 — — 100 — 2.5 — 15 — 0.6 Min. Typ. Max. — 32 — — 1000 — Preliminary Unit Notes Max. Unit 3.6 V — MΩ — pF — pF — V Unit Notes kHz ms 1 Freescale Semiconductor, Inc. ...
Page 29
... Read 1s All Blocks execution time rd1all t Read Once execution time rdonce t Program Once execution time pgmonce K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — 20 — 20 — 160 Min. Typ. ...
Page 30
... Table continues on the next page... Preliminary Max. Unit Notes 1600 μs 1 Typ. Unit 10 mA Max. Unit Notes 1 — years 2 — years 2 — years 2 — cycles 3 Min. Max. Unit 2.7 3.6 V — MHz SYS — MHz SYS — ns EZP_CK 5 — — ns Freescale Semiconductor, Inc. ...
Page 31
... Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DP3. K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors EP3 EP2 EP4 EP9 EP7 ...
Page 32
... Table continues on the next page... Preliminary Table 25 and Max. Unit Notes 3.6 V +100 mV 2 +100 DDA V V SSA V V REFH kΩ kΩ 4 18.0 MHz 5 12.0 MHz 6 818.330 Ksps Freescale Semiconductor, Inc. ...
Page 33
... For guidelines and examples of conversion rate calculation please download the ADC calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp Figure 10. ADC input impedance equivalency diagram K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1 Max. Typ. 37.037 — 361.402 = 1.0 MHz unless otherwise stated. Typical values are for ADCK SIMPLIFIED ...
Page 34
... MHz ±TBD ADC 4 LSB conversion ±1 clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) ±TBD 4 ADC LSB conversion ±0.5 clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) ±TBD Max 4 LSB averaging ±TBD ±TBD LSB ADIN V ±TBD DDA — 4 LSB ±0.5 Freescale Semiconductor, Inc. ...
Page 35
... )/2 REFH REFL 5. Input data is 1 kHz sine wave. FIGURE TBD Figure 11. Typical TUE vs. ADC conversion rate 12-bit single-ended mode K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = REFH DDA REFL 1 Min. Typ. ...
Page 36
... Min. Typ. — 590 — TBD Table continues on the next page... Preliminary Max. Unit Notes 3 DDA V V DDA — kΩ 4 IN+ to IN- — — — Ω 5 — µs 6 causes drop AS 1 Max. Unit Notes TBD μ TBD μA 3 Freescale Semiconductor, Inc. ...
Page 37
... V Maximum PP,DIFF differential input signal swing SNR Signal-to-noise • Gain=1 ratio • Gain=64 K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. TBD 0.98 TBD 1.99 TBD 3.97 TBD 7.95 TBD 15 ...
Page 38
... Average=32, f =500Hz in — bits 16-bit differential — bits mode, — bits f =500Hz in — bits — bits — bits — bits — bits — bits — bits — bits dB Typ. Max. Unit — 3.6 V — 200 μA Freescale Semiconductor, Inc. ...
Page 39
... Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level LSB = V /64 reference K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — V – 0.3 SS — ...
Page 40
... Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 1.3 1.6 1.9 2.2 Vin level (V) Preliminary HYSTCTR S etting 2.5 2.8 3.1 Freescale Semiconductor, Inc. ...
Page 41
... The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO small load capacitance (47 pF) can improve the bandwidth performance of the DAC K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1 ...
Page 42
... TBD DACR ±8 LSB 2 ±1 LSB 3 ±1 LSB 4 ±0.8 %FSR 5 ±0.6 %FSR — μV/C — ppm of FSR/C TBD μV/yr 250 Ω V/μs — — -80 dB kHz — — Freescale Semiconductor, Inc. ...
Page 43
... Calculated by a best fit curve from V Figure 15. Typical INL error vs. digital code K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors +100 mV to VREF−100 mV SS Preliminary 43 ...
Page 44
... V and temperature=25C DDA K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 44 Min. 1.71 −40 — Min. Typ. TBD 1.2 Table continues on the next page... Preliminary Max. Unit Notes 3.6 V 105 °C 100 nF Max. Unit Notes TBD V Freescale Semiconductor, Inc. ...
Page 45
... TBD Figure 17. Typical output vs.temperature TBD 6.7 Timers See General switching specifications. 6.8 Communication interfaces K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. TBD 1.198 — — — — — — ...
Page 46
... Table continues on the next page... Preliminary Typ. Max. Unit TBD TBD V — 2 μA 100 150 μA — 24.8 kΩ TBD 0.4 V Max. Unit Notes 5.5 V TBD μA TBD μA — nA TBD μA 120 3.6 V 3.6 V Freescale Semiconductor, Inc. ...
Page 47
... The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. ...
Page 48
... Description DS10 DS15 DS12 First data Data DS14 First data Data Preliminary DS4 Min. Max. Unit 1.71 3.6 V — 6.25 MHz — ns BCLK (t / SCK SCK/2) — — — — ns — — DS9 DS16 DS11 Last data Last data Freescale Semiconductor, Inc. ...
Page 49
... Table 39. Slave mode DSPI timing (high-speed mode) Num Operating voltage Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Description DS1 DS2 DS8 Data Last data First data ...
Page 50
... K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 50 Description DS10 DS15 DS12 First data Data DS14 First data Data Preliminary Min. Max. Unit — TBD ns 0 — — — ns — — DS9 DS16 DS11 Last data Last data Freescale Semiconductor, Inc. ...
Page 51
... SDHC input hold time THL SDHC_CLK Output SDHC_CMD Output SDHC_DAT[3:0] Input SDHC_CMD Input SDHC_DAT[3:0] K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Card input clock SD3 SD2 SD1 SD6 SD7 SD8 Figure 23. SDHC timing Preliminary Min ...
Page 52
... S in master (clocks driven) and slave 2 S master mode timing S10 2 S timing — master mode Preliminary Min. Max. Unit 2.7 3 SYS 45% 55% MCLK period — ns SYS 45% 55% BCLK period — -2.5 — ns — — — — S10 S8 Freescale Semiconductor, Inc. ...
Page 53
... DDTSI C Target electrode capacitance range ELE f Reference oscillator frequency REFmax f Electrode oscillator frequency ELEmax K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 42 slave mode timing S11 S12 S15 S16 S18 2 S timing — slave modes Min ...
Page 54
... Max. Unit Notes TBD pF TBD mV TBD μA 2 TBD μA 2 TBD % 3 TBD % 4 TBD % 5 — fF/count 6 — fF/count 7 16 bits 25 μs 8 — μA TBD μ μA, REFCHRG = 4 128, Max. Unit Notes 58 Hz — — 8000 pF 2 1.15 V 1.85 V — IREG Freescale Semiconductor, Inc. ...
Page 55
... Package dimensions are provided in package drawings. To find a package drawing search for the drawing’s document number: If you want the drawing for this package 80-pin LQFP 81-pin MAPBGA K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. Typ. — — — — ...
Page 56
... NOTE ALT1 ALT2 ALT3 ALT4 PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 PTE1 SPI1_SOUT UART1_RX SDHC0_D0 PTE2 SPI1_SCK UART1_CT SDHC0_DC S_b LK PTE3 SPI1_SIN UART1_RT SDHC0_CM S_b D PTE4 SPI1_PCS0 UART3_TX SDHC0_D3 PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 Preliminary ALT5 ALT6 ALT7 EzPort I2C1_SDA I2C1_SCL Freescale Semiconductor, Inc. ...
Page 57
... VDD • 39 VSS VSS VSS • 40 PTA18 EXTAL EXTAL • 41 PTA19 XTAL XTAL K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTA0 UART0_CT FTM0_CH5 S_b PTA1 UART0_RX FTM0_CH6 PTA2 UART0_TX FTM0_CH7 PTA3 UART0_RT FTM0_CH0 ...
Page 58
... SPI0_PCS1 UART1_RX FTM0_CH2 Preliminary ALT5 ALT6 ALT7 EzPort FTM1_QD_ LCD_P0 PHA FTM1_QD_ LCD_P1 PHB FTM0_FLT3 LCD_P2 FTM0_FLT0 LCD_P3 LCD_P8 LCD_P9 FTM0_FLT1 LCD_P10 FTM0_FLT2 LCD_P11 EWM_IN LCD_P12 EWM_OUT LCD_P13 _b FTM2_QD_ LCD_P14 PHA FTM2_QD_ LCD_P15 PHB LCD_P20 LCD_P21 LCD_P22 LCD_P23 Freescale Semiconductor, Inc. ...
Page 59
... LCD_P46/ ADC0_SE7 ADC0_SE7 b b • — VSS VSS VSS • 80 PTD7 LCD_P47 LCD_P47 K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTC4 SPI0_PCS0 UART1_TX FTM0_CH3 PTC5 SPI0_SCK LPT0_ALT2 PTC6 SPI0_SOUT PDB0_EXT RG PTC7 SPI0_SIN PTC8 ...
Page 60
... The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. The 81 MAPBGA ballmap assignments are currently being developed. K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 60 NOTE Preliminary Freescale Semiconductor, Inc. ...
Page 61
... PGA1_DM/ADC1_DM0/ADC0_DM3 VDDA 17 VREFHNC 18 19 VREFLNC 20 VSSA 9 Revision History The following table provides a revision history for this document. K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Figure 26. K40 80 LQFP Pinout Diagram Preliminary Revision History 60 VLL3NC 59 VSS 58 PTC3 57 PTC2 56 PTC1 ...
Page 62
... Corrected 81- and 104-pin package codes Added sections that were inadvertently removed in previous revision Reworded I footnote in "Voltage and Current Operating Requirements" IC table. Added paragraph to "Peripheral operating requirements and behaviors" section. Added "JTAG full voltage range electricals" table to the "JTAG electricals" section. Preliminary Freescale Semiconductor, Inc. ...
Page 63
... Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time ...