MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1127
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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14.8.21 DRAM Control Register 23 (HW_DRAM_CTL23)
This is a DRAM configuration register.
Address:
Re-
14.8.22 DRAM Control Register 24 (HW_DRAM_CTL24)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
EXTERNAL_CNT
Bit
INTERNAL_CNT
W
W
R
R
LOWPOWER_
LOWPOWER_
31
31
0
0
31 16
Field
Field
15 0
30
30
0
0
29
29
0
0
LOWPOWER_SELF_REFRESH_CNT
HW_DRAM_CTL23
HW_DRAM_CTL24
28
28
0
0
LOWPOWER_INTERNAL_CNT
The user should not use both automatic and manual modes for the various low power modes. All modes
should be entered automatically or all entered manually.
For all bits:
'b0 = Automatic entry into this mode is disabled. The user may enter this mode manually by setting the
associated lowpower_control bit.
'b1 = Automatic entry into this mode is enabled. The mode will be entered automatically when the proper
counters expire, and only if the associated lowpower_control bit is set.
Counts idle cycles to self-refresh with memory and controller clk gating.
Counts the number of idle cycles before memory self-refresh with memory and controller clock gating low
power mode.
Counts idle cycles to self-refresh with memory clock gating.
Counts the number of idle cycles before memory self-refresh with memory clock gating low power mode.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
HW_DRAM_CTL22 field descriptions (continued)
24
24
0
0
23
23
0
0
HW_DRAM_CTL23 field descriptions
800E_0000h base + 5Ch offset = 800E_005Ch
800E_0000h base + 60h offset = 800E_0060h
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
LOWPOWER_REFRESH_HOLD
LOWPOWER_EXTERNAL_CNT
Chapter 14 External Memory Interface (EMI)
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1127
0
0
0
0
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