MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1134
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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- Download datasheet (17Mb)
Programmable Registers
14.8.29 DRAM Control Register 31 (HW_DRAM_CTL31)
This is a DRAM configuration register.
Address:
1134
Reset
Reset
MAX_ROW_REG
MAX_COL_REG
MAX_CS_REG
OBSOLETE
Bit
Bit
W
W
R
R
RSVD2
RSVD1
18 16
15 12
31 24
Field
11 8
Field
7 4
3 0
31
15
0
0
HW_DRAM_CTL31
30
14
0
0
Maximum number of chip selects available. READ-ONLY
Displays the maximum number of chip selects configured for this EMI. This parameter is read-only.
Always write zeroes to this field.
Maximum width of memory address bus. READ-ONLY
Defines the maximum width of the memory address bus for the EMI.
This value can be used to set the addr_pins parameter. This parameter is read-only.
addr_pins = max_row_reg - <number of row bits in memory device>.
Always write zeroes to this field.
Maximum width of column address in DRAMs. READ-ONLY
Defines the maximum width of column address in the DRAM devices. This value can be used to set the
column_size parameter. This parameter is read-only.
column_size = max_col_reg - <number of column bits in memory device>.
Always write zeroes to this field.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL30 field descriptions (continued)
RSVD2
OBSOLETE
28
12
0
0
800E_0000h base + 7Ch offset = 800E_007Ch
HW_DRAM_CTL31 field descriptions
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
Description
Description
23
0
0
7
22
0
0
6
21
0
5
0
RSVD3
RSVD1
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
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