MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1220
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Programmable Registers
Address:
14.8.161 DRAM Control Register 172 (HW_DRAM_CTL172)
This is a DRAM configuration register.
Address:
1220
Reset
Reset
Reset
AXI5_BDW_
AXI4_BDW_
DLL_RST_
Bit
Bit
Bit
OVFLOW
OVFLOW
W
W
W
R
R
R
RSVD2
RSVD1
DELAY
31 25
23 17
Field
15 0
24
16
31
15
31
0
0
0
HW_DRAM_CTL171
HW_DRAM_CTL172
30
14
30
0
0
0
Always write zeroes to this field.
Port 5 behavior when bandwidth maximized.
Always write zeroes to this field.
Port 4 behavior when bandwidth maximized.
Minimum number of cycles required for DLL reset.
Sets the number of cycles that the reset must be held asserted for the DLL.
29
13
29
0
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RSVD2
RSVD4
28
12
28
0
0
0
HW_DRAM_CTL171 field descriptions
800E_0000h base + 2ACh offset = 800E_02ACh
800E_0000h base + 2B0h offset = 800E_02B0h
27
11
27
0
0
0
26
10
26
0
0
0
25
25
0
0
0
9
DLL_RST_DELAY
24
24
0
0
0
8
Description
23
23
0
0
0
7
22
22
0
0
0
6
21
21
0
5
0
0
RSVD1
RSVD3
20
20
0
4
0
0
Freescale Semiconductor, Inc.
19
19
0
0
0
3
18
18
0
0
0
2
17
17
0
0
0
1
RESYNC_
DLL
16
16
0
0
0
0
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