MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1427
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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20.2.4 Shadow Registers and Hardware Capability Bus
The on-chip hardware capability bus is generated using a direct connection to the shadow
registers HW_OCOTP_HWCAP0–5 and HW_OCOTP_HWSWCAP. The bits are copied
from the OTP on reset. They can be modified until either
HW_OCOTP_LOCK_HWSW_SHADOW or
HW_OCOTP_LOCK_HWSW_SHADOW_ALT is set. In addition, HW_OCOTP_SWCAP
and HW_OCOTP_LOCK are also shadowed into physical registers immediately after reset.
The user can force a reload of the shadow registers (including HW_OCOTP_LOCK) without
having to reset the device, which is useful for debugging code. To force a reload:
HW_OCOTP_CTRL_RELOAD_SHADOWS can be set at any time. There is no need to
wait for HW_OCOTP_CTRL_BUSY or HW_OCOTP_CTRL_ERROR to be clear.
Freescale Semiconductor, Inc.
• Set HW_OCOTP_CTRL_RELOAD_SHADOWS.
• Wait for HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_RELOAD_SHADOWS
• Attempting to write to the shadow registers while the shadows are being reloaded will
• Attempting to write to a shadow register that is locked will result in the setting of
• In the case of HW_OCOTP_CTRL_BUSY being set due to an active write, the controller
• In the case where HW_OCOTP_CTRL_RD_BANK_OPEN is set, the shadow reload
• In all cases, the controller will clear HW_OCOTP_CTRL_RELOAD_SHADOWS after
to be cleared by the controller.
result in the setting of HW_OCOTP_CTRL_ERROR. In addition, the register will not
take the attempted write (yielding to the reload instead).
HW_OCOTP_CTRL_ERROR.
will perform the bank opening and shadow reloading immediately after the completion
of the write.
will be performed immediately after the banks are closed by the software (by clearing
HW_OCOTP_CTRL_RD_BANK_OPEN). It should be noted that BUSY will take
approximately 33 HCLK cycles to clear, so polling for HW_OCOTP_CTRL_BUSY
immediately after clearing HW_OCOTP_CTRL_RD_BANK_OPEN is not
recommended.
the successful completion of the operation.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 20 On-Chip OTP (OCOTP) Controller
1427
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