MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1545
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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24.3.12 UART Masked Interrupt Status Register (HW_UARTDBG_MIS)
The MIS register is the Masked Interrupt Status Register. It is a read-only register. On a
read this register gives the current masked status value of the corresponding interrupt. A
write has no effect. All the bits except for the modem status interrupt bits (bits 3 to 0) are
cleared to 0 when reset. The modem status interrupt bits are undefined after reset.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
UNAVAILABLE
Bit
Bit
Reserved
W
W
R
R
OEMIS
BEMIS
PEMIS
FEMIS
RTMIS
31 16
15 11
Field
10
9
8
7
6
31
15
0
0
HW_UARTDBG_MIS
30
14
0
0
The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are
always unavailable.
This bitfield is reserved.
Reserved, read as zero, do not modify.
Overrun Error Masked Interrupt Status.
Break Error Masked Interrupt Status.
Parity Error Masked Interrupt Status.
Framing Error Masked Interrupt Status.
Receive Timeout Masked Interrupt Status.
RESERVED
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_UARTDBG_MIS field descriptions
8007_4000h base + 40h offset = 8007_4040h
27
11
0
0
26
10
0
0
25
0
0
9
UNAVAILABLE
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
Chapter 24 Debug UART (DUART)
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
1545
16
0
0
0
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