MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1684
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1684 of 2327
- Download datasheet (17Mb)
Programmable Registers
26.4.30 ENET MAC Transmit FIFO Almost Full Threshold Register
Address:
Re-
26.4.31 ENET MAC Transmit Inter-Packet Gap Register
Address:
Re-
1684
set
set
Bit
Bit
W
W
R
R
TX_ALMOST_
31
31
RSRVD0
RSRVD0
0
0
FULL
Field
31 8
Field
31 5
7 0
30
30
0
0
29
29
0
0
HW_ENET_MAC_TX_ALMOST_FULL 800F_0000h base + 1A8h offset = 800F_
01A8h
HW_ENET_MAC_TX_IPG_LENGTH
01ACh
(HW_ENET_MAC_TX_ALMOST_FULL)
(HW_ENET_MAC_TX_IPG_LENGTH)
28
28
0
0
Reserved bits. Write as 0.
Value, in 64-Bit words, of the Transmit FIFO almost full threshold. The number of bits, K, is Log2 of the
Transmit FIFO depth.
A minimum value of 6 is required to have correct ff_tx_rdy deassertion before the fifo overflows. If a lower
value is set, the FIFO will overflow when ff_tx_rdy is deasserted, hence there would be no time for the
application to react properly.
A recommended value of at least 8 should be set allowing a latency of 2 clock cycles to the application. If
more latency is required the value can be increased as necessary (latency=TX_ALMOST_FULL-5).
Note that a FIFO overflow is a fatal error and requires a global reset on the transmit datapath or at least
deassertion of ETHER_EN.
Reserved bits. Write as 0.
27
27
0
0
26
26
0
HW_ENET_MAC_TX_ALMOST_FULL field descriptions
0
HW_ENET_MAC_TX_IPG_LENGTH field descriptions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
0
0
22
22
0
0
21
21
0
0
RSRVD0
20
20
0
0
19
19
0
RSRVD0
0
18
800F_0000h base + 1ACh offset = 800F_
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
TX_ALMOST_FULL
6
0
0
5
5
TX_IPG_LENGTH
0
0
4
4
3
1
3
1
0
1
2
2
0
0
1
1
0
0
0
0
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