MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1846
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1846 of 2327
- Download datasheet (17Mb)
Programmable Registers
29.9.2 ENET SWI Scratch Register (HW_ENET_SWI_SCRATCH)
The Scratch Register provides a memory location to test the register access. It returns all
data written to it in inverted form.
Address:
Re-
29.9.3 ENET SWI Port Enable Bits. (HW_ENET_SWI_PORT_ENA)
Port Enable Bits. Two bits per port. The transmit and receive direction for each port can be
independently enabled. When the transmit direction is enabled a frame can be forwarded
to the port. When disabled, all frames forwarded to the port are discarded. When the receive
direction is enabled the port is selected and a frame is accepted if it indicates data available.
If the receive direction is disabled the input is ignored and never selected for frame reception.
Address:
1846
set
Reset
Bit
MEMORY_DATA
W
R
SCRATCH
Bit
31
W
0
R
Field
31 0
Field
31 0
30
0
31
0
29
0
HW_ENET_SWI_PORT_ENA 800F_8000h base + 8h offset = 800F_8008h
HW_ENET_SWI_SCRATCH
28
0
30
0
HW_ENET_SWI_LOOKUP_MEMORY_START field descriptions
Memroy cell.
The Scratch Register provides a memory location to test the register access. It returns all data written to it
in inverted form.
27
0
26
0
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_ENET_SWI_SCRATCH field descriptions
24
0
28
0
23
0
22
0
27
0
21
0
800F_8000h base + 4h offset = 800F_8004h
20
0
26
0
19
0
RSRVD1
18
25
0
0
17
0
SCRATCH
16
24
0
0
15
0
Description
Description
23
14
0
0
13
0
22
12
0
0
11
0
21
0
10
0
0
9
20
0
0
8
Freescale Semiconductor, Inc.
0
7
19
0
0
6
0
5
18
0
0
4
3
0
17
0
0
2
0
1
16
0
0
0
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