MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 6

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Table 4
6
Pulse Width Modulator (PWM)
Application UART (AUART): Interfaces supported
Synchronous Serial Port (SSP): Supported through dedicated pins
I
SPDIF
SAIF
FlexCAN
LCD interface
High-speed ADC
LRADC (touchscreen, keypad...)
Ethernet MAC and switch
Universal Serial Bus (USB)
2
C
Mnemonic
APBHDMA
APBXDMA
AUART(5)
ARM9 or
ARM926
Block
describes the digital and analog modules of the device.
ARM926EJ-S
CPU
UART
interface
Application
AHB to APBH
AHB to APBX
Block Name
Bridge with
Bridge with
DMA
DMA
i.MX28 Applications Processor Data Sheet for Consumer Products, Rev. 0
System control The AHB to APBH bridge with DMA includes the AHB-to-APB PIO bridge for
System control The AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for
ARM ®
Connectivity
peripherals
Subsystem
Function
Table 4. i.MX28 Digital and Analog Modules
Table 3. i.MX28 Functions (continued)
memory-mapped I/O to the APB devices, as well a central DMA facility for
devices on this bus. The bridge provides a peripheral attachment bus running
on the AHB’s HCLK. (The ‘H’ in APBH denotes that the APBH is synchronous
to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.)
The DMA controller transfer read and write data to and from each peripheral
on APBH bridge.
memory-mapped I/O to the APB devices, as well a central DMA facility for
devices on this bus. The AHB-to-APBX bridge provides a peripheral
attachment bus running on the AHB’s XCLK. (The ‘X’ in APBX denotes that
the APBX runs on a crystal-derived clock, as compared to APBH, which is
synchronous to HCLK.) The DMA controller transfer reads and writes data to
and from each peripheral on APBX bridge.
The ARM926 Platform consists of the ARM926EJ-S™ core and the ETM
real-time debug modules. It contains the 16-Kbyte L1 instruction cache,
32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM.
Each of the UART modules supports the following serial data
transmit/receive protocols and configurations:
• 7- or 8-bit data words, one or two stop bits, programmable parity (even,
• Programmable baud rates up to 3.25 MHz. This is a higher maximum
odd, or none)
baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard
and previous Freescale UART modules. 16-byte FIFO on Tx and 16-byte
FIFO on Rx supporting auto-baud detection
Brief Description
5 dedicated / 8 with muxing
4 dedicated / 5 with muxing
3 dedicated / 4 with muxing
1 dedicated / 2 with muxing
1
2
2
24 bits
Yes
Yes
2 MACs with switch
2
BGA289
Freescale Semiconductor