CC-ACC-MMK-2443 Digi International, CC-ACC-MMK-2443 Datasheet - Page 32
CC-ACC-MMK-2443
Manufacturer Part Number
CC-ACC-MMK-2443
Description
MCU, MPU & DSP Development Tools CC9M 2443 Multimedia App Kit
Manufacturer
Digi International
Datasheet
1.CC-ACC-ADD-2443.pdf
(135 pages)
Specifications of CC-ACC-MMK-2443
Processor To Be Evaluated
S3C2443
Data Bus Width
32 bit
Interface Type
UART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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C h a p t e r 1
The S3C2443 UART includes programmable baud rates, infrared (IR) transmit/receive,
one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity
checking.
Each UART provides a baud-rate generator, transmitter, receiver and a control unit.
The baud-rate generator can be clocked by PCLK or EPLLCLK/n. UEXTCLK (external
input clock) is used on the module as GPIO. The transmitter and the receiver contain
64-byte FIFOs and data shifters. Data is written to FIFO and then copied to the
transmit shifter before being transmitted. The data is then shifted out by the
transmit data pin (TxDn). Meanwhile, received data is shifted from the receive data
pin (RxDn), and then copied to FIFO from the shifter.
The S3C2443 UART block supports also infra-red (IR) transmission and reception,
which can be selected by setting the Infra-red-mode bit in the UART line control
register (ULCONn).
There are four UART baud rate divisor registers including UBRDIV0, UBRDIV1, UBRDIV2
and UBRDIV3 in the UART block. The value stored in the baud rate divisor register
(UBRDIVn) and dividing slot register(UDIVSLOTn), are used to determine the serial
Tx/Rx clock rate (baud rate) as follows:
DIV_VAL = (SRCCLK / (baud rate x 16 ) ) -1
Where DIV_VAL should be from 1 to (216-1) and SRCCLK is either PCLK or divided EPLL
clock.
DIV_VAL can be programmed in the S3C2443 registers the following way:
DIV_VAL = UBRDIVn + (num of 1's in UDIVSLOTn)/16
ConnectCore 9M 2443 Hardware Reference
32
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