WM8974GEFL/V Wolfson Microelectronics, WM8974GEFL/V Datasheet
WM8974GEFL/V
Specifications of WM8974GEFL/V
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WM8974GEFL/V Summary of contents
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... APPLICATIONS • Digital Still Camera Audio Codec • Wireless VoIP and other communication device handsets / headsets • Portable audio recorder • General Purpose low power audio CODEC at http://www.wolfsonmicro.com/enews/ WM8974 Production Data, Rev 4.5, September 2008 Copyright ©2008 Wolfson Microelectronics plc ...
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WM8974 DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 TERMINOLOGY ............................................................................................................ 8 SIGNAL TIMING REQUIREMENTS .......................................................................9 SYSTEM CLOCK TIMING ............................................................................................. 9 ...
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... Production Data PIN CONFIGURATION TOP VIEW ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8974GEFL/V -40°C to +85°C WM8974GEFL/RV -40°C to +85°C Note: Reel Quantity = 3,500 w PACKAGE MOISTURE SENSITIVITY 24-lead QFN (4x4x0.9mm) (Pb-free) 24-lead QFN (4x4x0.9mm) (Pb-free, tape and reel) WM8974 PACKAGE BODY ...
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WM8974 PIN DESCRIPTION PIN NO NAME 1 Analogue Output MICBIAS 2 AVDD Supply 3 AGND Supply 4 DCVDD Supply 5 DBVDD Supply 6 DGND Supply 7 ADCDAT Digital Output 8 Digital Input DACDAT 9 FRAME Digital Input / Output 10 ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8974 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, T otherwise stated. PARAMETER Microphone Inputs (MICN, MICP) Full-scale Input Signal Level (Note 1) – note this changes with AVDD Mic PGA equivalent input ...
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Production Data Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, T otherwise stated. PARAMETER Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load) Signal to Noise Ratio (Note ...
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WM8974 TERMINOLOGY 1. MICN input only in single ended microphone configuration. Maximum input signal to MICP without distortion is -3dBV. 2. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up ...
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Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note 1: PLL pre-scaling and PLL N and ...
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WM8974 Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT ...
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Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T MCLK = ...
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WM8974 CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low ...
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Production Data DEVICE DESCRIPTION INTRODUCTION The WM8974 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include digital still cameras with ...
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WM8974 CONTROL INTERFACES To allow full software control over all its features, the WM8974 offers a choice wire MPU control interface fully compatible and an ideal partner for a wide range of industry standard ...
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Production Data Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic input) REGISTER ADDRESS R44 Input Control The input PGA is enabled by the IPPGAEN register bit. REGISTER ADDRESS R2 Power Management 2 w BIT LABEL ...
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WM8974 INPUT PGA VOLUME CONTROL The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the AUX amplifier to the PGA output are ...
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Production Data In mixer mode (AUXMODE=1) the on-chip input resistor is bypassed, this allows the user to sum in multiple inputs with the use of external resistors. variations through this path from part to part due to the variation of ...
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WM8974 The MICP path to the BOOST stage is controlled by the MICP2BOOSTVOL[2:0] register bits. When MICP2BOOSTVOL=000 this input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB ...
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Production Data Figure 9 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8974 uses a multi-bit, oversampled sigma-delta ADC channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ...
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WM8974 The polarity of the output signal can also be changed under software control using the ADCPOL register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which ...
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Production Data PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. These coefficients should be converted to 2’s complement numbers to determine the register ...
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WM8974 NOTCH FILTER WORKED EXAMPLE The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth 1000 100 48000 ...
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Production Data INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8974 has an automatic PGA gain control circuit, which can function as an input peak limiter automatic level control (ALC). The Automatic Level Control (ALC) provides continuous ...
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WM8974 REGISTER ADDRESS R34 (22h) ALC Control 3 Table 14 ALC Control Registers w BIT LABEL DEFAULT 8 ALCZC 0 (zero cross off) 7:4 ALCHLD 0000 [3:0] (0ms) 8 ALCMODE 0 7:4 ALCDCY 0011 [3:0] (26ms/6dB) 0011 (5.8ms/6dB) 3:0 ALCATK ...
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Production Data When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits. NORMAL MODE In normal mode, the ALC ...
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WM8974 LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is ...
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Production Data NORMAL MODE ALCMODE = 0 (Normal Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 0 (Normal Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 15 ...
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WM8974 LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 16 ALC ...
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Production Data MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC ...
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WM8974 ALCMIN 000 001 010 011 100 101 110 111 Table 19 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing ...
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Production Data Figure 14 ALCLVL w WM8974 PD, Rev 4.5, September 2008 31 ...
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WM8974 Figure 15 ALC Hold Time ALCHLD Table 21 ALC Hold Time Values w t (s) HOLD 0000 0 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s Production ...
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Production Data PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ...
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WM8974 Figure 16 ALC Operation Above Noise Gate Threshold w Production Data PD, Rev 4.5, September 2008 34 ...
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Production Data Figure 17 Noise Gate Operation OUTPUT SIGNAL PATH The WM8974 output signal paths consist of digital application filters, up-sampling filters, a Hi-Fi DAC, analogue mixers, speaker and mono output drivers. The digital filters and DAC are enabled by ...
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WM8974 The analogue output from the DAC can then be mixed with the AUX analogue input and the ADC analogue input. The mix is fed to the output drivers, SPKOUTP/N, and MONOOUT. MONOOUT: can drive a 16Ω or 32Ω headphone ...
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Production Data The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters a multi-bit, sigma-delta DAC, which converts high quality analogue audio signal. The multi-bit ...
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WM8974 VOLUME BOOST The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume ...
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Production Data REGISTER ADDRESS R24 DAC digital limiter control 1 R25 DAC digital limiter control 2 Table 28 DAC Digital Limiter Control w BIT LABEL DEFAULT 3:0 LIMATK 0010 7:4 LIMDCY 0011 8 LIMEN 0 3:0 LIMBOOST 0000 6:4 LIMLVL ...
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WM8974 GRAPHIC EQUALISER A 5-band graphic EQ is provided, which can be applied to the ADC or DAC path under control of the EQMODE register bit. REGISTER ADDRESS R18 EQ Control 1 Table 29 EQ DAC or ADC Path Select ...
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Production Data REGISTER ADDRESS R21 EQ Band 4 Control Table 33 EQ Band 4 Control REGISTER ADDRESS R22 EQ Band 5 Gain Control Table 34 EQ Band 5 Control GAIN REGISTER 00000 00001 00010 …. (1dB steps) 01100 01101 11000 ...
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WM8974 ANALOGUE OUTPUTS The WM8974 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and are capable of driving up to 1.5V rms signals ...
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Production Data REGISTER ADDRESS R49 Output control R1 Power management 1 Table 36 Output Boost Control SPKBOOST/ MONOBOOST 0 1 Table 37 Output Boost Stage Details SPKOUTP/SPKOUTN OUTPUTS The SPKOUT pins can drive a single bridge tied 8 Ω speaker ...
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WM8974 REGISTER ADDRESS R54 Speaker volume control Table 39 SPKOUT Volume Control ZERO CROSS TIMEOUT A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update ...
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Production Data REGISTER ADDRESS R56 Mono mixer control R40 Bypass path attenuation control Table 41 Mono Mixer Control ENABLING THE OUTPUTS Each analogue output of the WM8974 can be separately enabled or disabled. The analogue mixer associated with each output ...
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WM8974 REGISTER ADDRESS R49 Table 43 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This buffer can be enabled using the BUFIOEN register bit. If the ...
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Production Data OUTPUT SWITCH When the device is configured with a 2-wire interface the CSB/GPIO pin can be used as a switch control input to automatically disable the speaker outputs and enable the mono output. For example when a line ...
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WM8974 HEADPHONE OUTPUT The speaker outputs can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors coupled without any capacitor. Headphone Output using DC Blocking Capacitors: Figure 23 Recommended Headphone Output Configurations When DC blocking ...
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Production Data DIGITAL AUDIO INTERFACES The audio interface has four pins: • • • • The clock signals BCLK, and FRAME can be outputs when the WM8974 operates as a master, or inputs when slave (see Master ...
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WM8974 Figure 26 Right Justified Audio Interface (assuming n-bit word length mode, the MSB is available on the second rising edge of BCLK following a FRAME transition. The other bits up to the LSB are then ...
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Production Data REGISTER ADDRESS R4 Audio interface control Table 47 Audio Interface Control Audio Interface Control The register bits controlling audio format, word length and master / slave mode are summarised below. Each audio interface can be controlled individually. Register ...
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WM8974 REGISTER ADDRESS R6 Clock generation control Table 48 Clock Control Note that the setting MCLKDIV=000 and BCLKDIV=000 must not be used simultaneously. LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data ...
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Production Data REGISTER ADDRESS R5 Companding control Table 49 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: µ-law (where µ=255 for the U.S. and Japan): ...
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WM8974 Figure 29 u-Law Companding Figure 30 A-Law Companding AUDIO SAMPLE RATES The WM8974 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times ...
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Production Data REGISTER ADDRESS R7 Additional control Table 51 Sample Rate Control MASTER CLOCK AND PHASE LOCKED LOOP (PLL) The WM8974 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8974 audio ...
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WM8974 The PLL frequency ratio EXAMPLE: MCLK=12MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide the PLL and a selectable divide by ...
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Production Data GENERAL PURPOSE INPUT/OUTPUT The CSB/GPIO pin can be configured to perform a variety of useful tasks by setting the GPIOSEL register bits. The GPIO is only available in 2 wire mode. Note that SLOWCLKEN must be enabled when ...
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WM8974 2-WIRE SERIAL CONTROL MODE The WM8974 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the ...
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Production Data Note: • DCVDD should be greater than or equal to 1.9V when using the PLL. • DCVDD is less than or equal to DBVDD RECOMMENDED POWER UP/DOWN SEQENCE In order powered up and down using one of the ...
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WM8974 V por_on V pora Power Supply DGND POR No Power POR Undefined POR Clocks ADC Internal State Power down (Note 1) AVDD/2 Analogue Inputs ADCDAT pin (Note 3) ADCEN bit INPPGAEN bit VMIDSEL/ BIASEN bits (Note ...
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Production Data Notes: 1. The analogue input pin charge time, t time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. 2. The analogue input pin discharge time, t ...
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WM8974 SYMBOL t line_midrail_on t line_midrail_off t hp_midrail_on t hp__midrail_off Table 58 Typical POR Operation (typical values, not tested) Notes: 1. The lineout charge time, t time is dependent upon the value of VMID decoupling capacitor and VMID pin input ...
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Production Data POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. ...
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WM8974 Table 59 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit. REGISTER BIT BUFDCOPEN MONOEN PLLEN MICBEN BIASEN BUFIOEN VMIDSEL BOOSTEN INPPGAEN ADCEN MONOEN SPKPEN SPKNEN MONOMIXEN SPKMIXEN DACEN Table 62 AVDD Supply Current w ...
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Production Data REGISTER MAP REGISTER B8 ADDR NAME B[15:9] DEC HEX 0 00 Software Reset 1 01 Power manage’t BUFDCOP Power manage’ Power manage’ Audio Interface BCP 5 ...
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WM8974 REGISTER B8 ADDR NAME B[15:9] DEC HEX 56 38 MONO mixer ctrl 0 REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked “s ...
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Production Data REGISTER BIT LABEL ADDRESS 7 MONOEN 6 SPKNEN 5 SPKPEN 4 3 MONOMIXEN 2 SPKMIXEN 1 0 DACEN 4 (04h) 8 BCP 7 FRAMEP 6:5 WL 4:3 FMT 2 DACLRSWAP 1 ADCLRSWAP 0 5 (05h) 8:5 4:3 DAC_COMP ...
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WM8974 REGISTER BIT LABEL ADDRESS 2:1 ADC_COMP 0 LOOPBACK 6 (06h) 8 CLKSEL 7:5 MCLKDIV 4:2 BCLKDIV (07h) 8:4 3 (08h) 8:6 5:4 OPCLKDIV w DEFAULT DESCRIPTION 00 ADC companding 00=off 01=reserved 10=µ-law ...
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Production Data REGISTER BIT LABEL ADDRESS 3 GPIOPOL 2:0 GPIOSEL 9 (09h) 8:0 10 (0Ah) 8:7 6 DACMU 5:4 DEEMPH 3 DACOSR128 2 AMUTE 1 0 DACPOL 11 (0Bh) 8 7:0 DACVOL 12 (0Ch) 8:0 13 (0Dh) 8:0 14 (0Eh) ...
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WM8974 REGISTER BIT LABEL ADDRESS 0 ADCPOL 15 (0Fh) 8 7:0 ADCVOL 16 (10h) 8:0 17 (11h) 8:0 18 (12h) 8 EQMODE 7 6:5 EQ1C 4:0 EQ1G 19 (13h) 8 EQ2BW 7 6:5 EQ2C 4:0 EQ2G 20 (14h) 8 EQ3BW ...
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Production Data REGISTER BIT LABEL ADDRESS 6:5 EQ5C 4:0 EQ5G 24 (18h) 8 LIMEN 7:4 LIMDCY 3:0 LIMATK 25 (19h) 8:7 6:4 LIMLVL w DEFAULT DESCRIPTION 01 Band 5 Cut-off Frequency: 00=5.3kHz 01=6.9kHz 10=9kHz 11=11.7kHz 01100 Band 5 Gain Control. ...
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WM8974 REGISTER BIT LABEL ADDRESS 3:0 LIMBOOST 27 (1Bh) 8 NFU 7 NFEN 6:0 NFA0[13:7] 28 (1Ch) 8 NFU 7 6:0 NFA0[6:0] 29 (1Dh) 8 NFU 7 6:0 NFA1[13:7] 30 (1Eh) 8 NFU 7 6:0 NFA1[6:0] 32 (20h) 8 ALCSEL ...
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Production Data REGISTER BIT LABEL ADDRESS 33 (21h) 8 ALCZC 7:4 ALCHLD 3:0 ALCLVL 34 (22h) 8 ALCMODE 7:4 ALCDCY 3:0 ALCATK 35 (23h) 8:4 3 NGEN w DEFAULT DESCRIPTION 0 ALC zero cross detection disabled 1 = ...
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WM8974 REGISTER BIT LABEL ADDRESS 2:0 NGTH 36 (24h) 8:5 4 PLLPRESCALE 3:0 PLLN[3:0] 37 (25h) 8:6 5:0 PLLK[23:18] 38 (26h) 8:0 PLLK[17:9] 39 (27h) 8:0 PLLK[8:0] 40 (28h) 8:3 2 MONOATTN 1 SPKATTN 0 44 (2Ch) 8 MBVSEL 7:4 ...
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Production Data REGISTER BIT LABEL ADDRESS 6 INPPGAMUTE 5:0 INPPGAVOL 47 (2Fh) 8 PGABOOST 7 6:4 MICP2BOOSTVOL 000 3 2:0 AUX2BOOSTVOL 000 49 (31h) 8:4 3 MONOBOOST 2 SPKBOOST 1 TSDEN 0 VROI 50 (32h) 8:6 5 AUX2SPK 4:2 1 ...
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WM8974 REGISTER BIT LABEL ADDRESS 54 (36h SPKZC 6 SPKMUTE 5:0 SPKVOL 56 (38h) 8:7 6 MONOMUTE 5:3 2 AUX2MONO 1 BYP2MONO 0 DAC2MONO w DEFAULT DESCRIPTION 0 Speaker Volume control zero cross enable Change gain ...
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Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 63 Digital Filter Characteristics ...
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WM8974 DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) Figure 36 DAC Digital Filter Frequency Response ADC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) ...
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Production Data DE-EMPHASIS FILTER RESPONSES -10 0 2000 4000 6000 8000 10000 Frequency (Hz) Figure 40 De-emphasis Frequency Response (32kHz ...
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WM8974 HIGHPASS FILTER The WM8974 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter 3.7Hz. frequency -10 -15 -20 ...
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Production Data 5-BAND EQUALISER The WM8974 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 50 to Figure 63 show the frequency responses of each filter with a ...
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WM8974 -10 - Frequency (Hz) Figure 55 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BW -10 - ...
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Production Data -10 - Frequency (Hz) Figure 58 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BW -10 - ...
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WM8974 Figure 63 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show the cumulative effect of all bands with ...
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Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 64 Recommended External Components w WM8974 PD, Rev 4.5, September 2008 85 ...
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WM8974 PACKAGE DIAGRAM FL: 24 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW A3 C SIDE VIEW SEATING PLANE Exposed ...
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... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...