ispPAC-CLK5620AV-01TN100I Lattice, ispPAC-CLK5620AV-01TN100I Datasheet

Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I

ispPAC-CLK5620AV-01TN100I

Manufacturer Part Number
ispPAC-CLK5620AV-01TN100I
Description
Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I
Manufacturer
Lattice

Specifications of ispPAC-CLK5620AV-01TN100I

Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Maximum Operating Temperature
70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPPAC-CLK5620AV-01TN100I
Manufacturer:
LATTICE
Quantity:
210
Part Number:
ISPPAC-CLK5620AV-01TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
June 2008
Features
■ 8MHz to 400MHz Input/Output Operation
■ Low Output to Output Skew (<50ps)
■ Low Jitter Peak-to-Peak
■ Up to 20 Programmable Fan-out Buffers
■ Fully Integrated High-Performance PLL
■ Precision Programmable Phase Adjustment
Product Family Block Diagram
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
(Skew) Per Output
* Input Available only on ispClock5620A
• Programmable output standards and individual
• Programmable output impedance
• Programmable slew rate
• Up to 10 banks with individual V
• Programmable lock detect
• Multiply and divide ratio controlled by
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
• 16 settings; minimum step size 156ps
• Up to +/- 12ns skew range
• Coarse and fine adjustment modes
*
*
enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL,
- 40 to 70 Ω in 5 Ω increments
- 1.5V, 1.8V, 2.5V, 3.3V
- Input divider (1 to 40)
- Feedback divider (1 to 40)
- Five output dividers (2 to 80)
- Locked to VCO frequency
LVDS, LVPECL, Differential HSTL, SSTL
Internal/External
M
N
Feedback
Select
LOCK DETECT
FREQUENCY
DETECTOR
PHASE/
CCO
INTERFACE
MEMORY
E
2
JTAG
PLL CORE
CMOS
&
FILTER
and GND
INTERNAL FEEDBACK PATH
Management Logic
0
VCO
Multiple Profile
ispClock 5600A Family
In-System Programmable, Enhanced Zero-Delay
1-1
1
Clock Generator with Universal Fan-Out Buffer
■ Up to Five Clock Frequency Domains
■ Flexible Clock Reference and External
■ All Inputs and Outputs are Hot Socket
■ Four User-programmable Profiles Stored in
■ Full JTAG Boundary Scan Test In-System
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial
■ 100-pin and 48-pin TQFP Packages
■ Applications
2
BYPASS
Feedback Inputs
Compliant
E
Programming Support
(-40 to 85°C) Temperature Ranges
MUX
3
• Programmable input standards
• Clock A/B selection multiplexer
• Feedback A/B selection multiplexer
• Programmable termination
• Supports both test and multiple operating
• Circuit board common clock generation and
• PLL-based frequency generation
• High fan-out clock buffer
• Zero-delay clock buffer
2
CMOS
configurations
distribution
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, SSTL
DIVIDERS
OUTPUT
®
V0
V1
V2
V3
V4
Memory
ROUTING
OUTPUT
MATRIX
CONTROL
SKEW
Data Sheet DS1019
DRIVERS
OUTPUT
DS1019_01.4

Related parts for ispPAC-CLK5620AV-01TN100I

ispPAC-CLK5620AV-01TN100I Summary of contents

Page 1

... Input Available only on ispClock5620A © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

Page 2

... Lattice Semiconductor General Description and Overview The ispClock5610A and ispClock5620A are in-system-programmable high-fanout enhanced zero delay clock gen- erators designed for use in high performance communications and computing applications. The ispClock5610A provides single-ended or five differential clock outputs, while the ispClock5620A provides single- ended or 10 differential clock outputs. Each pair of outputs may be independently confi ...

Page 3

... Lattice Semiconductor Figure 1-2. ispClock5620A Functional Block Diagram PS0 PS1 Profile Select Control REFSEL REFA+ INPUT REFA- DIVIDER 0 M REFVTT (1-40) 1 REFB+ REFB- FEEDBACK N DIVIDER (1-40) FBKSEL FBKA FBKA- 0 FBKVTT 1 FBKB+ FBKB- LOCK RESET PLL_BYPASS SGATE GOE OUTPUT ENABLE CONTROLS LOCK ...

Page 4

... Lattice Semiconductor Absolute Maximum Ratings Core Supply Voltage -0.5 to 5.5V CCD PLL Supply Voltage -0.5 to 5.5V CCA JTAG Supply Voltage -0.5 to 5.5V CCJ Output Driver Supply Voltage V CCO Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V 1 Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Junction Temperature with power supplied . . . . . . -40 to 130° ...

Page 5

... Lattice Semiconductor 2 E CMOS Memory Write/Erase Characteristics Parameter Erase/Reprogram Cycles Performance Characteristics – Power Supply Symbol Parameter 3 I Core Supply Current CCD 3 I Analog Supply Current CCA Output Driver Supply Current I CCO (per Bank) I JTAG I/O Supply Current (static) CCJ 1. Supply current consumed by each bank, both outputs active, 5pF load. ...

Page 6

... Lattice Semiconductor DC Electrical Characteristics – LVDS Symbol Parameter V Common Mode Input Voltage ICM V Differential Input Threshold THD V Input Voltage IN V Output High Voltage OH V Output Low Voltage OL V Output Voltage Differential OD ΔV Change in V Between H and Output Voltage Offset OS ΔV Change in V ...

Page 7

... Lattice Semiconductor Electrical Characteristics – Differential SSTL2 Symbol Parameter V Output Supply Voltage CCO V DC Differential Input Voltage Swing SWING(DC Input Differential Voltage SWING(AC) Input Pair Differential Crosspoint V IX Voltage TCKD Clock Duty Cycle Electrical Characteristics – Differential HSTL Symbol Parameter V Output Supply Voltage ...

Page 8

... Lattice Semiconductor Switching Characteristics – Timing Adders for I/O Modes Adder Type 2 t Input Adders IOI LVTTL_in Using LVTTL Standard LVCMOS18_in Using LVCMOS 1.8V Standard LVCMOS25_in Using LVCMOS 2.5V Standard LVCMOS33_in Using LVCMOS 3.3V Standard SSTL18_in Using SSTL18 Standard SSTL2_in Using SSTL2 Standard ...

Page 9

... Lattice Semiconductor Output Rise and Fall Times – Typical Values Slew 1 (Fastest) Output Type LVTTL 0.54 0.76 LVCMOS 1.8V 0.75 0.69 LVCMOS 2.5V 0.57 0.69 LVCMOS 3.3V 0.55 0.77 SSTL18 0.55 0.40 SSTL2 0.50 0.40 SSTL3 0.50 0.45 HSTL 0.60 0.45 eHSTL 0 ...

Page 10

... Lattice Semiconductor Figure 1-5. LVDS/LVPECL Termination Load 50Ω/3" 50Ω/1" ispCLOCK 50Ω/3" 50Ω/1" Figure 1-6. Differential HSTL/SSTL Termination Load ispCLOCK Interface Circuit 3pF (parasitic) 0.1U 34Ω 33.2Ω 44.2Ω 0.1U 33.2Ω 34Ω 3pF (parasitic) 50Ω/3" ...

Page 11

... Lattice Semiconductor Programmable Input and Output Termination Characteristics Symbol Parameter R Input Resistance Output Resistance OUT 1. Guaranteed by characterization. Conditions V Voltage CCO Rin=40Ω setting Rin=45Ω setting Rin=50Ω setting Rin=55Ω setting Rin=60Ω setting Rin=65Ω setting Rin=70Ω setting VCCO=3 ...

Page 12

... Lattice Semiconductor Performance Characteristics – PLL Symbol Parameter Reference and feedback input f f REF, FBK frequency range t Reference and feedback input CLOCKHI, t clock HIGH and LOW times CLOCKLO t Reference and feedback input RINP, t rise and fall times FINP M M-divider range DIV ...

Page 13

... Lattice Semiconductor Timing Specifications Skew Matching Symbol Parameter Between any two identically configured and loaded t Output-output Skew SKEW outputs regardless of bank. Programmable Skew Control Symbol Parameter t Skew Control Range SKRANGE SK Skew Steps per range STEPS 2 t Skew Step Size ...

Page 14

... Lattice Semiconductor Timing Specifications (Cont.) Boundary Scan Logic Symbol t TCK (BSCAN Test) Clock Cycle BTCP t TCK (BSCAN Test) Pulse Width High BTCH t TCK (BSCAN Test) Pulse Width Low BTCL t TCK (BSCAN Test) Setup Time BTSU t TCK (BSCAN Test) Hold Time ...

Page 15

... Lattice Semiconductor Timing Diagrams Figure 1-8. Erase (User Erase or Erase All) Timing Diagram VIH TMS VIL SU1 SU1 CKH GKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 1-9. Programming Timing Diagram VIH TMS VIL SU1 H t CKH VIH TCK VIL ...

Page 16

... Lattice Semiconductor Typical Performance Characteristics I vs. f CCD (Normalized to 800MHz) 1.2 1 0.8 0.6 0.4 0.2 0 300 400 500 f (MHz) VCO Typical Skew Error vs. Setting (Skew Mode = FINE Skew Setting # Cycle-Cycle Jitter vs. VCO Frequency V 320 370 420 470 VCO Frequency (MHz) *PFD = Phase/Frequency Detector VCO 1 ...

Page 17

... Lattice Semiconductor Typical Performance Characteristics (Cont.) Typical Phase Jitter vs. VCO Frequency PFD MHz 16 320 370 420 470 VCO Frequency Typical Period Jitter vs. VCO Frequency PFD = 80 MHz 320 370 420 470 VCO Frequency *PFD = Phase/Frequency Detector Detailed Description PLL Subsystem The ispClock5600A provides an integral phase-locked-loop (PLL) which may be used to generate output clock sig- nals at lower, higher, or the same frequency as a user-supplied input reference signal. The core functions of the PLL are an edge-sensitive phase detector, a programmable loop fi ...

Page 18

... The option for which mode to use is programmable and may be set using PAC-Designer software (available from the Lattice website at www.latticesemi.com). In Phase Lock Detect mode the lock detector asserts the LOCK signal as soon as a lock condition is determined. ...

Page 19

... Lattice Semiconductor The input, or M-Divider prescales the input reference frequency, and can be programmed with integer values over the range 40. To achieve low levels of output jitter best to use the smallest M-Divider value possible. The feedback, or N-Divider prescales the feedback frequency and like the M-Divider, can also be programmed with integer values ranging from 1 to 40. Each one of the fi ...

Page 20

... Lattice Semiconductor Note: Bypassing M- and N-Dividers also results in reducing the number of output frequency combinations gener- ated from a single reference clock input. PLL_BYPASS Mode The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the output of the M-Divider is routed directly to the inputs of the V-Dividers ...

Page 21

... Lattice Semiconductor Figure 1-14. ispClock5600A Clock Reference and Feedback Input Structure (REFA+/- Pair Shown) ispClock5600A REFA+ REFA- REFVTT The following usage guidelines are suggested for interfacing to supported logic families. LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V) The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi- nal of the input pair (e.g. REFA+). The ‘ ...

Page 22

... Lattice Semiconductor pairs is not used, tie the unused pins REF+ and REF- to GND. In addition, if external feedback is not used, tied FBVTT to GND. One important point to note is that the termination supplies must have low impedance and be able to both source and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive divider network, which has an impedance comparable to the resistors used commodity-type linear voltage regulators, which can only source current ...

Page 23

... Lattice Semiconductor LVDS/Differential LVPECL The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be engaged and set to 50Ω. The associated REFVTT or FBKVTT pin, however, should be left unconnected. This cre- ates a floating 100Ω differential termination resistance across the input terminals. The LVDS termination configura- tion is shown in Figure 1-18. Figure 1-18. LVDS Input Receiver Confi ...

Page 24

... Lattice Semiconductor actual impedance required will be a function of the driver used to generate the signal and the transmission medium used (PCB traces, connectors and cabling). The ispClock5600A’s ability to adjust input impedance over a range of 40Ω to 70Ω allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to swap out components ...

Page 25

... Lattice Semiconductor Figure 1-20. ispClock5600A Output Driver and Skew Control OEX OEY GOE V-Dividers 2 E CMOS 2 E CMOS OEX OEY GOE From V-Dividers 2 E CMOS On / Off Skew Adjust From Skew Adjust On / Off 2 E CMOS (a) Single-ended Configuration Output Driver and Skew Control ...

Page 26

... Lattice Semiconductor Each of the ispClock5600A’s output driver banks can be configured to support the following logic outputs: • LVTTL • LVCMOS (1.8V, 2.5V, 3.3V) • SSTL2 • SSTL3 • HSTL • eHSTL • LVDS • Differential LVPECL (3.3V) • Differential SSTL18, SSTL2, SSTL3, HSTL, eHSTL To provide LVTTL, LVCMOS, SSTL2, SSTL3, HSTL and eHSTL outputs, the CMOS output drivers in each bank are enabled ...

Page 27

... Lattice Semiconductor Figure 1-22 shows a typical configuration for the ispClock5600A’s output driver when configured to drive SSTL2, SSTL3, HSTL or eHSTL loads. The ispClock5600A’s output impedance should be set to 40Ω for driving SSTL2 or SSTL3 loads and to the ≈20Ω setting for driving HSTL and eHSTL. The far end of the transmission line must be ter- minated to an appropriate VTT voltage through a 50Ω ...

Page 28

... Lattice Semiconductor When GOE is HIGH, all output drivers are forced into a high-Z state, regardless of any internal configuration. When GOE is LOW, the output drivers may also be enabled or disabled on an individual basis, and optionally controlled by the OEX and OEY pins. Internal E enabled (when GOE pin is LOW), never enabled (permanently off), or selectively enabled by the state of either OEX or OEY ...

Page 29

... Lattice Semiconductor For fine skew mode, When an output driver is programmed to support a differential output mode, a single skew setting is applied to both the BANKxA+ and BANKxB- signals. When the output driver is configured to support a single-ended output stan- dard, each of the two single-ended outputs may be assigned independent skews. ...

Page 30

... Lattice Semiconductor coarse mode has a value greater than 40, as the corresponding fine skew mode setting would be greater than 80, which is not supported. Output Skew Matching and Accuracy Understanding the various factors which relate to output skew is essential for realizing optimal skew performance in the ispClock5600A family of devices. ...

Page 31

... Lattice Semiconductor Figure 1-26. Output Timing Adders for Logic Type (a) and Output Slew Rate (b) LVDS Output ( IOO LVTTL Output (T = 0.395ns) IOO (a) Similarly, when one changes the slew rate of an output, the output slew rate adders (t the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are measured. For example, in the case of outputs confi ...

Page 32

... Lattice Semiconductor Internal Feedback Mode In addition to supporting the use of external feedback to close the phase-locked loop, ispClock5620A also provides the option of using an internal feedback path for this function. This feature is useful for minimizing external connec- tions and routing in situations where one can attempt to compensate for external signal path delays using the pro- grammable skew feature of the internal feedback path. Profi ...

Page 33

... Thermal characteristics of the packages employed by Lattice Semiconductor may be found in the document Thermal Management which may be obtained at www.latticesemi.com. The maximum current consumption of the digital and analog core circuitry for ispClock5620A is 150mA worst case ...

Page 34

... PAC-Designer operation. PAC-Designer is available for download from the Lattice website at www.latticesemi.com. The PAC-Designer schematic window, shown in Figure 1- 29 provides access to all configurable ispClock5600A elements via its graphical user interface. All analog input and output pins are represented. Static or non-confi ...

Page 35

... Lattice Semiconductor Figure 1-29. PAC-Designer Design Entry Screen In-System Programming The ispClock5600A is an In-System Programmable (ISP™) device. This is accomplished by integrating all 2 E CMOS configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored ...

Page 36

... Evaluation Fixture Included in the basic ispClock5600A Design Kit is an engineering prototype board that can be connected to the parallel port using a Lattice ispDOWNLOAD ispClock5600A and can be used in real time to check circuit operation as part of the design process. Input and out- put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5600A for a given application ...

Page 37

... Lattice Semiconductor Figure 1-31. ispClock5600A TAP Registers TDI TAP Controller Specifics The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller design ...

Page 38

... Lattice Semiconductor Figure 1-32. TAP States Test-Logic-Rst Run-Test/Idle Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state ...

Page 39

... The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The bit code for this instruction is defined by Lattice as shown in Table 1-6. The EXTEST (external test) instruction is required and will place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. The bit code of this instruc- tion is defi ...

Page 40

... E Configured In addition to the four instructions described above, there are 20 unique instructions specified by Lattice for the ispClock5600A. These instructions are primarily used to interface to the various user registers and the E non-volatile memory. Additional instructions are used to control or monitor other features of the device, including boundary scan operations ...

Page 41

... Lattice Semiconductor VERIFY_INCR – This instruction copies the E umn register and then auto-increments the value of the address register. The device must already be in program- ming mode for this instruction to execute. DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ispClock5600A for a read cycle. PROGRAM_USERCODE – ...

Page 42

... Lattice Semiconductor Pin Descriptions Pin Name Description VCCO_0 Output Driver ‘0’ VCC VCCO_1 Output Driver ‘1’ VCC VCCO_2 Output Driver ‘2’ VCC VCCO_3 Output Driver ‘3’ VCC VCCO_4 Output Driver ‘4’ VCC VCCO_5 Output Driver ‘5’ VCC VCCO_6 Output Driver ‘ ...

Page 43

... Lattice Semiconductor Pin Descriptions (Continued) Pin Name Description VCCD Digital Core VCC GNDD Digital GND VCCJ JTAG interface VCC REFA+ Clock Reference A positive input REFA- Clock Reference A negative input REFB+ Clock Reference B positive input REFB- Clock Reference B negative input REFSEL Clock Reference Select input (LVCMOS) ...

Page 44

... Lattice Semiconductor Detailed Pin Descriptions VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1µ ...

Page 45

... Lattice Semiconductor GOE – Global output enable. This pin drives all outputs to a high-impedance state when it is pulled HIGH. GOE also controls the internal feedback buffer, so that bringing GOE high will cause the PLL to lose lock. PS0, PS1 – These input pins are used to select one of four user-defined configuration profiles for the device. ...

Page 46

... Lattice Semiconductor Package Diagrams 48-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR 0. SECTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND DETERMINED AT DATUM PLANE DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS ...

Page 47

... Lattice Semiconductor 100-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR TOP VIEW SECTION B-B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND DETERMINED AT DATUM PLANE DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS ...

Page 48

... CLK5610A CLK5620A Ordering Information Conventional Packaging Part Number ispPAC-CLK5610AV-01T48C ispPAC-CLK5620AV-01T100C Part Number ispPAC-CLK5610AV-01T48I ispPAC-CLK5620AV-01T100I Lead-Free Packaging Part Number ispPAC-CLK5610AV-01TN48C ispPAC-CLK5620AV-01TN100C Part Number ispPAC-CLK5610AV-01TN48I ispPAC-CLK5620AV-01TN100I Commercial Clock Outputs Supply Voltage 10 3.3V 20 3.3V Industrial Clock Outputs Supply Voltage 10 3.3V 20 3.3V Commercial Clock Outputs ...

Page 49

... Lattice Semiconductor Package Options ispClock5610A: 48-pin TQFP VCCO_0 BANK_0B BANK_0A GNDO_0 VCCO_1 BANK_1B BANK_1A GNDO_1 VCCO_2 BANK_2B BANK_2A GNDO_2 ispClock5600A Family Data Sheet ispPAC CLK5610AV-01T48C 1-49 36 VCCJ 35 TDO 34 LOCK 33 VCCD 32 GNDO_4 31 BANK_4A 30 BANK_4B 29 VCCO_4 28 GNDO_3 27 BANK_3A 26 BANK_3B 25 VCCO_3 ...

Page 50

... BANK_1A 9 GNDO_1 10 VCCO_2 11 BANK_2B 12 BANK_2A 13 GNDO_2 14 VCCO_3 15 BANK_3B 16 BANK_3A 17 GNDO_3 18 VCCO_4 19 BANK_4B 20 BANK_4A 21 GNDO_4 22 n/c 23 n/c 24 n/c 25 ispClock5600A Family Data Sheet ispPAC-CLK5620AV-01T100C 1-50 75 n/c 74 VCCJ 73 TDO 72 LOCK 71 VCCD 70 GNDO_9 69 BANK_9A 68 BANK_9B 67 VCCO_9 66 GNDO_8 BANK_8A 65 64 BANK_8B 63 VCCO_8 62 GNDO_7 61 BANK_7A 60 BANK_7B 59 VCCO_7 ...

Page 51

... June 2008 01.4 Change Summary Previous Lattice releases. Added min. and max. values to Timing Adders for I/O Modes table. Added min. and max. values to PLL Bypass Mode operation table. Added Phase Lock Detect feature description. Added M-Divider and N-Divider Bypass feature description. ...

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