XRT75R12DIB-F Exar Corporation, XRT75R12DIB-F Datasheet

Page 1

... MRing_n Monitor DMO_n ICT P N ART UMBER XRT75R12DIB Exar Corporation 48720 Kato Road, Fremont CA, 94538 Bellcore GR-499 specifications. Also, the jitter attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. 3 The XRT75R12D provides a Parallel Microprocessor Interface for programming and control. ...

Page 2

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FEATURES RECEIVER 3 R Technology (Reconfigurable, Redundancy) On chip Clock and Data Recovery circuit for high input jitter tolerance Meets E3/DS3/STS-1 Jitter Tolerance Requirement Detects and Clears LOS as per ...

Page 3

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 GENERAL DESCRIPTION.............................................................................................................. 1 A ............................................................................................................................................................... 1 PPLICATIONS XRT 75R12D.................................................................................................................................. 1 IGURE LOCK IAGRAM OF THE ORDERING INFORMATION .................................................................................................................... 1 F ..................................................................................................................................................................... 2 EATURES T I ...

Page 4

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER ABLE ITTER RANSFER PECIFICATION 4.3 JITTER ATTENUATOR ................................................................................................................................... ............................................................................................................................................. 30 ABLE ITTER RANSFER ASS ASKS F 16. J ...

Page 5

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 ABLE HANNEL EVEL NTERRUPT NABLE T 25 ABLE HANNEL EVEL NTERRUPT TATUS T 26 ABLE ...

Page 6

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 56 IGURE LLUSTRATION OF URST OF 8.5.4 PHASE TRANSIENTS............................................................................................................................................... 110 F 57. I "P -T IGURE LLUSTRATION OF HASE RANSIENT 8.5.5 87-3 PATTERN.......................................................................................................................................................... 111 F 58. ...

Page 7

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 PIN DESCRIPTIONS ( BY FUNCTION SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS IGNAL AME YPE P4 TxON F22 TxCLK0 AA22 TxCLK1 H22 TxCLK2 ...

Page 8

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS IGNAL AME YPE C25 TxNEG0 AB25 TxNEG1 H23 TxNEG2 W23 TxNEG3 H24 TxNEG4 Y26 TxNEG5 H3 TxNEG6 ...

Page 9

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS IGNAL AME YPE C23 MTip0 AD23 MTip1 D19 MTip2 AC19 MTip3 D15 MTip4 AC15 MTip5 E11 ...

Page 10

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS IGNAL AME YPE D25 RLOS0 O AD25 RLOS1 G23 RLOS2 AA24 RLOS3 J24 RLOS4 U24 RLOS5 J3 ...

Page 11

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS IGNAL AME YPE F23 RxNEG/LCV0 O AC26 RxNEG/LCV1 F24 RxNEG/LCV2 U23 RxNEG/LCV3 L23 RxNEG/LCV4 T24 RxNEG/LCV5 ...

Page 12

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER RECEIVE LINE SIDE PINS IGNAL AME YPE B22 RTip0 I AE22 RTip1 B18 RTip2 AE18 RTip3 A14 RTip4 AF14 RTip5 D13 RTip6 AC13 RTip7 ...

Page 13

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 CLOCK INTERFACE IGNAL AME YPE R5 SFM_EN I R1 E3Clk I T1 DS3Clk I U1 STS-1Clk/12M I C26 CLKOUT0 O W22 CLKOUT1 K23 ...

Page 14

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER GENERAL CONTROL PINS IGNAL AME YPE P3 TEST **** AE25 TRST I TMS AB23 I AB5 TCK I AB4 TDI I AE2 TDO O ...

Page 15

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 MICROPROCESSOR PARALLEL INTERFACE - IGNAL AME YPE K25 Addr0 I M22 Addr1 M23 Addr2 M24 Addr3 K26 Addr4 L26 Addr5 M26 Addr6 N26 ...

Page 16

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER POWER SUPPLY PINS AME IN UMBERS RVDD0 D22 RVDD1 AC22 RVDD2 D18 RVDD3 AC18 RVDD4 E15 RVDD5 AB15 RVDD6 E12 RVDD7 AB12 RVDD8 A9 RVDD9 ...

Page 17

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 GROUND PINS AME IN UMBERS RGND0 A22 RGND1 AF22 RGND2 A18 RGND3 AF18 RGND4 E14 RGND5 AB14 RGND6 E13 RGND7 AB13 RGND8 D9 RGND9 ...

Page 18

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER ABLE IST UMBER AME B8 A1 AGND B9 A2 AGND B10 A3 DVDD B11 A4 ...

Page 19

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 AME IN F5 TxCLK10 J25 F22 TxCLK0 J26 F23 RxNEG/LCV0 K1 F24 RxNEG/LCV2 K2 F25 DVDD K3 F26 DGND K4 G1 TxCLK6 K5 ...

Page 20

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER AME Y1 TxNEG7 AB15 Y2 DGND AB16 Y3 RxPOS9 AB17 Y4 TxCLK9 AB18 Y5 DVDD AB19 Y22 DVDD AB20 Y23 TxCLK3 AB21 Y24 RxPOS3 ...

Page 21

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 AME AF13 AVDD AF14 RTip5 AF15 TGND5 AF16 DVDD AF17 DVDD AF18 RGND3 AF19 TGND3 AF20 DVDD AF21 DVDD AF22 RGND1 AF23 TGND1 AF24 ...

Page 22

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FUNCTIONAL DESCRIPTION The XRT75R12D is a twelve channel fully integrated Line Interface Unit featuring EXAR’s R (Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications. independent Receivers, Transmitters and Jitter Attenuators in a ...

Page 23

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 2.0 CLOCK SYNTHESIZER The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks used to drive the LIU. The reference clock used ...

Page 24

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 2.1 Clock Distribution Network cards that are designed to support multiple line rates which are not configured for single frequency mode should ensure that a clock is applied to the ...

Page 25

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 3.0 THE RECEIVER SECTION The receiver is designed so that the LIU can recover clock and data from an attenuated line signal caused by cable loss or flat loss ...

Page 26

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 3.3 Receive Equalizer The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation 900 feet of coaxial cable (1300 feet for E3). ...

Page 27

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 3.5 LOS (Loss of Signal) Detector 3.5.1 DS3/STS-1 LOS Condition A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on ...

Page 28

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER IGURE OSS OF IGNAL EFINITION FOR RTIP/ RRing RLOS Output Pin 0 UI 3.5.4 Interference Tolerance For E3 mode, ITU-T G.703 Recommendation specifies that the ...

Page 29

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T ABLE M C ODE ABLE E3 DS3 STS NTERFERENCE ARGIN EST ESULTS ENGTH TTENUATION NTERFERENCE ...

Page 30

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 3.5.5 Muting the Recovered Data with LOS condition: When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the internal master clock outputs ...

Page 31

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 4.0 JITTER There are three fundamental parameters that describe circuit performance relative to jitter Jitter Tolerance Jitter Transfer Jitter Generation 4 ITTER OLERANCE Jitter tolerance is a ...

Page 32

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 14 IGURE NPUT ITTER OLERANCE 1.5 0.3 0.15 0.1 0.01 0.03 JITTER FREQUENCY (kHz) 4.1.2 E3 Jitter Tolerance Requirements ITU-T G.823 ...

Page 33

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 ABLE ITTER MPLITUDE VERSUS I J NPUT ATE S TANDARD ( / ) 34368 ITU-T G.823 1.5 44736 GR-499 ...

Page 34

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER R ATE M ASK ( ) KBITS G.823 34368 ETSI-TBR-24 44736 GR-499, Cat I GR-499, Cat II GR-253 CORE 51840 GR-253 CORE The jitter attenuator within the XRT75R12D meets the ...

Page 35

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 5.0 DIAGNOSTIC FEATURES 5.1 PRBS Generator and Detector The XRT75R12D contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for diagnostic purpose. With the PRBSEN_n bit = ...

Page 36

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 5.2 LOOPBACKS The XRT75R12D offers three loopback modes for diagnostic purposes. The loopback modes are selected via the RLB_n and LLB_n bits n the Channel control registers select the loopback ...

Page 37

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 5.2.2 DIGITAL LOOPBACK When the Digital Loopback is selected, the transmit clock TxClk_n and transmit data inputs (TxPOS_n & TxNEG_n are looped back and output onto the RxClk_n, RxPOS_n ...

Page 38

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 5.3 TRANSMIT ALL ONES (TAOS) Transmit All Ones (TAOS) can be set by setting the TAOS_n control bits to “1” in the Channel control registers. When the TAOS is set, ...

Page 39

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 6.0 THE TRANSMITTER SECTION The transmitter is designed so that the LIU can accept serial data from a local device, encode the data properly, and then output an analog ...

Page 40

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F IGURE t RTX TxClk TPData or TNData TTIP or TRing SYMBOL PARAMETER TxClk Duty Cycle TxClk Frequency E3 DS-3 STS-1 t TxClk Rise Time (10% to 90%) RTX t ...

Page 41

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 IGURE UAL AIL ATA ORMAT Data 0 TPData TNData TxClk 6.1 Transmit Clock The Transmit Clock applied via TxClk_n pins, for the selected ...

Page 42

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 28. HDB3 E F IGURE NCODING ORMAT TClk TPDATA 1 0 Line Signal 1 6.3 Transmit Pulse Shaper The Transmit Pulse Shaper converts the B3ZS encoded ...

Page 43

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 6.4 E3 line side parameters The XRT75R12D line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation. The pulse mask as ...

Page 44

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER ABLE RANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS PARAMETER Occurence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time ...

Page 45

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 IME IN NIT NTERVALS < < -0.68 T 0.26 < < 0.26 T 1.4 T 10: STS ABLE RANSMITTER INE P ARAMETER T ...

Page 46

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 32 IGURE RANSMIT UPUT ULSE 1.2 1 0.8 0.6 0.4 0 IME IN NIT NTERVALS < < -0.85 T -0.36 < ...

Page 47

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T 12: DS3 T L ABLE RANSMITTER INE P ARAMETER T RANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude ...

Page 48

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 6.5 Transmit Drive Monitor This feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on the line or a defective line ...

Page 49

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 7.0 MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports communication between the local microprocessor (µP) and the LIU. The XRT75R12D supports a parallel interface asynchronously or synchronously timed to ...

Page 50

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 7 ICROPROCESSOR NTERFACE The LIU may be configured into different operating modes and have its performance monitored by software through a standard microprocessor using data, address ...

Page 51

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 7 SYNCHRONOUS AND YNCHRONOUS Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The synchronous mode requires an input clock (PCLK) to ...

Page 52

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T ABLE S P YMBOL ARAMETER t Valid Address to CS Falling Edge Falling Edge to RD Assert Assert to RDY Assert 2 NA ...

Page 53

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T ABLE S P YMBOL ARAMETER t Valid Address to CS Falling Edge Falling Edge to RD Assert Assert to RDY Assert 2 ...

Page 54

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 7.3 Register Map T 17: C ABLE OMMAND DDRESS OMMAND EGISTER ( ECIMAL 0x00 CR0 0x01 CR1 0x02 CR2 0x03 CR3 0x04 CR4 0x05 ...

Page 55

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T 17: C ABLE OMMAND DDRESS OMMAND EGISTER ( ECIMAL 0x1D 0x1E 0x1F 0x20 0x21 CR33 0x22 CR34 0x23 CR35 0x24 CR36 0x25 ...

Page 56

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 17: C ABLE OMMAND DDRESS OMMAND EGISTER ( ECIMAL 0x3B CR59 0x3C CR60 0x3D 0x3E 0x3F 0x40 0x41 CR65 0x42 CR66 0x43 CR67 ...

Page 57

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T 17: C ABLE OMMAND DDRESS OMMAND EGISTER ( ECIMAL 0x59 0x5A CR90 0x5B CR91 0x5C CR92 0x5D 0x5E 0x5F 0x60 CR96 0x61 ...

Page 58

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 17: C ABLE OMMAND DDRESS OMMAND EGISTER ( ECIMAL 0x78 0x75 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 CR128 0x81 CR129 0x82 ...

Page 59

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T 17: C ABLE OMMAND DDRESS OMMAND EGISTER ( ECIMAL 0x95 CR149 0x96 CR150 0x97 CR151 0x98 0x99 0x9A CR154 0x9B CR155 0x9C ...

Page 60

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 17: C ABLE OMMAND DDRESS OMMAND EGISTER ( ECIMAL 0xB3 CR179 0xB4 CR180 0xB5 CR181 0xB6 CR182 0xB7 CR183 0xB8 0xB9 0xBA CR186 ...

Page 61

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T 17: C ABLE OMMAND DDRESS OMMAND EGISTER ( ECIMAL 0xD1 CR209 0xD2 CR210 0xD3 CR211 0xD4 CR212 0xD5 CR213 0xD6 CR214 0xD7 ...

Page 62

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 17: C ABLE OMMAND DDRESS OMMAND EGISTER ( ECIMAL 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF5 0xF9 0xFA 0xFB 0xFC ...

Page 63

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 THE GLOBAL/CHIP-LEVEL REGISTERS The register set, within the XRT75R12D contains ten global or chip-level registers. These registers control operations in more than one channel or apply to the complete ...

Page 64

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 20: APS/R ABLE EDUNDANCY Reserved Reserved RxON AME YPE N UMBER 7,6 Reserved 5 ...

Page 65

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T 22: APS/R ABLE EDUNDANCY Reserved Reserved RxON AME YPE N UMBER 7,6 Reserved ...

Page 66

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 23 ABLE HANNEL EVEL Reserved Reserved Channel 5 Interrupt Enable R/W Register - CR96 (Address Location = 0x60) B ...

Page 67

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 ABLE HANNEL EVEL Reserved Reserved Channel 11 Interrupt Enable R/W REGISTER - CR224 (ADDRESS LOCATION = ...

Page 68

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 25 ABLE HANNEL EVEL Reserved Reserved Channel 5 Interrupt Status R/O Register - CR97 (Address Location = 0x61) ...

Page 69

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 ABLE HANNEL EVEL Reserved Reserved Channel 11 Interrupt Status R/O Register - CR225 (Address Location = ...

Page 70

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 28 ABLE HIP EVISION R/O R/O R Register - CR111 (Address Location = 0x6F B N ...

Page 71

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 THE PER-CHANNEL REGISTERS The XRT75R12D consists of 120 per-Channel Registers (12 channels and 10 registers per channel). presents the overall Register Map with the Per-Channel Registers unshaded. REGISTER DESCRIPTION ...

Page 72

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 30 ABLE OURCE EVEL NTERRUPT Reserved UMBER AME Reserved ...

Page 73

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 UMBER AME 1 Change of LOS R/W Condition Interrupt Enable 0 Change of DMO R/W Condition Interrupt Enable D YPE Change of the Receive ...

Page 74

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 31: XRT75R12D R ABLE EGISTER Reserved OURCE EVEL NTERRUPT TATUS ...

Page 75

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 OURCE EVEL NTERRUPT TATUS UMBER AME 1 Change of LOS RUR Condition Interrupt Status 0 Change of DMO RUR ...

Page 76

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 32: XRT75R12D R ABLE EGISTER Reserved Loss of PRBS Digital LOS Pattern Sync Defect Declared R/O R ...

Page 77

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 LARM TATUS EGISTER HANNEL UMBER AME 5 Digital LOS Defect Declared 4 Analog LOS Defect Declared A L ...

Page 78

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER LARM TATUS EGISTER HANNEL UMBER AME 3 FL Alarm Declared 2 Receive LOL Condi- tion Declared ...

Page 79

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 LARM TATUS EGISTER HANNEL UMBER AME 1 Receive LOS Defect Condition Declared 0 Transmit DMO Con- dition Declared ...

Page 80

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 33: XRT75R12D R ABLE EGISTER Reserved Internal Transmit Drive Monitor R RANSMIT ONTROL EGISTER HANNEL N ...

Page 81

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 RANSMIT ONTROL EGISTER HANNEL UMBER AME 2 TAOS 1 TxCLKINV 0 TxLEV ...

Page 82

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 34: XRT75R12D R ABLE EGISTER Reserved Disable DLOS Detector R ECEIVE ONTROL EGISTER HANNEL N B ...

Page 83

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 ECEIVE ONTROL EGISTER HANNEL UMBER AME 1 Receive Monitor R/W Mode Enable 0 Receive Equalizer R/W Enable A ...

Page 84

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 35: XRT75R12D R ABLE EGISTER Reserved PRBS Enable Ch_n R HANNEL ONTROL EGISTER HANNEL N B ...

Page 85

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 HANNEL ONTROL EGISTER HANNEL UMBER AME 4 RLB_n R/W 3 LLB_n R/W 2 E3_n R ...

Page 86

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER HANNEL ONTROL EGISTER HANNEL UMBER AME 1 DS3 STS- SR/DR_n DDRESS ...

Page 87

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T 36: XRT75R12D R MAP ABLE EGISTER Reserved ITTER TTENUATOR ONTROL EGISTER ...

Page 88

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 37: XRT75R12D R ABLE EGISTER A DDRESS OCATION 0x0- APST IER0 ISR0 AS0 0 1- IER1 ISR1 AS1 X 0x2- IER2 ISR2 AS2 0x3- IER3 ...

Page 89

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T 39: XRT75R12D R ABLE EGISTER A DDRESS OCATION 0x7- 0x8- IER6 ISR6 AS6 APST 0 9- IER7 ISR7 AS7 X 0xA- IER8 ISR8 AS8 ...

Page 90

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 41: XRT75R12D R ABLE EGISTER A DDRESS OCATION 0xE- CIE CIS 0xF ABLE RROR OUNTER OLDING ...

Page 91

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 8.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU The LIU with D-SYNC is very similar to the non D-SYNC LIU in that they both contain Jitter Attenuator blocks within ...

Page 92

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER transported across the SDH network (from one PTE to the PTE at the other end of the SDH network). Once this SDH signal arrives at the remote PTE, this DS3 ...

Page 93

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 A detailed discussion on how to design with and configure the LIU device such that the end-system will meet these Intrinsic Jitter and Wander requirements SONET system, ...

Page 94

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 8.2.1.1 A Brief Description of an STS-1 Frame In order to be able to describe how a DS3 signal is asynchronously mapped into an STS-1 SPE important to ...

Page 95

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 IGURE IMPLE LLUSTRATION OF THE APACITY YTES ESIGNATED 3 Bytes TOH Since the TOH bytes occupy the first three byte columns ...

Page 96

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 40 IGURE HE YTE ORMAT OF THE 3 Byte Columns Rows ...

Page 97

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 IGURE HE YTE ORMAT OF THE 3 Byte Columns Rows ...

Page 98

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 42 IGURE LLUSTRATION OF THE 1 Byte Rows ...

Page 99

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 IGURE N LLUSTRATION OF ELCORDIA STS-1 SPE AN • For DS3 Mapping, the STS-1 SPE has the following structure ...

Page 100

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER Figure 44 presents an alternative illustration of Telcordia GR-253-CORE's recommendation on how to asynchronously map DS3 data into an STS-1 SPE. In this case, the STS-1 SPE bit-format is expressed ...

Page 101

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 The Ideal Case (e.g., with no frequency offsets) The 44.736Mbps + 1 ppm Case The 44.736MHz - 1ppm Case Throughout each of these cases, we will discuss how the ...

Page 102

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER In this case, this DS3 signal (which has now been mapped into STS-1) will be transported across the SONET network. As this STS-1 signal arrives at the "Destination PTE", this ...

Page 103

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 IGURE N LLUSTRATION OF THE DS3 WHEN MAPPING IN A SIGNAL THAT HAS A BIT RATE OF Source Source PTE PTE 44.736Mbps + 1ppm What ...

Page 104

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER Whenever these "positive-stuffing" events occur then (for these particular STS-1 SPEs) the SPE will carry only 5591 DS3 data bits (e.g., in this case, only 2 Stuff Opportunity bits will ...

Page 105

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 8.3 Jitter/Wander due to Pointer Adjustments In the previous section, we described how a DS3 signal is asynchronously-mapped into SONET, and we also defined "Mapping/De-mapping" jitter. In this section, ...

Page 106

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 49 IGURE HE IT FORMAT OF THE J1 REFLECTING THE LOCATION OF THE H1 Byte MSB Figure 50 relates the contents within ...

Page 107

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 8.3.2 Pointer Adjustments within the SONET Network The word SONET stands for "Synchronous Optical NETwork. This name implies that the entire SONET network is synchronized to a single clock ...

Page 108

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 51 IGURE N LLUSTRATION OF AN Clock Domain operating At frequency f1 STS-1 Data_IN STS-1 Clock_f1 In the "Slip Buffer, the "input" STS-1 data (labeled "STS-1 Data_IN") ...

Page 109

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 b. The "Transmitting" Network Equipment will notify the remote terminal of this byte-stuffing event, by invert- ing certain bits within the "pointer word" (within the H1 and H2 bytes) ...

Page 110

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER b. The "Transmitting" Network Element will notify the remote terminal of this "negative-stuff" event by inverting certain bits within the "pointer word" (within the H1 and H2 bytes) that are ...

Page 111

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 8.3.4 Why are we talking about Pointer Adjustments? The overall SONET network consists of numerous "Synchronization Islands" consequence, whenever a SONET signal is being transmitted from one ...

Page 112

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER In this application, these Mapper devices can be thought of as multi-channel devices. For example, an STS-3 Mapper can be viewed as a 3-Channel DS3/STS-1 to STS-3 Mapper IC. Similarly, ...

Page 113

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T 43: S "C ABLE UMMARY OF ATEGORY T ELCORDIA S S CENARIO CENARIO D N ESCRIPTION UMBER Continuous Pattern A4 Continuous Add A5 Continuous Cancel ...

Page 114

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 8.5.3 Pointer Burst Figure 56 presents an illustration of the "Pointer Burst" Pointer Adjustment Scenario per Telcordia GR-253- CORE IGURE LLUSTRATION OF URST OF Pointer Adjustment ...

Page 115

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Phase Transient - Pointer Adjustment" scenario must ...

Page 116

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 59. I 87-3 A IGURE LLUSTRATION OF THE 43 Pointer Adjustments T Telcordia GR-253-CORE defines an "87-3 Add" Pointer Adjustment, as the "87-3 Continuous" Pointer Adjustment pattern, with an ...

Page 117

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 Telcordia GR-253-CORE defines an "87-3 Cancel" Pointer Adjustment, as the "87-3 Continuous" Pointer Adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in Figure ...

Page 118

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 62 IGURE LLUSTRATION OF ONTINUOUS Continuous Pointer Adjustments T Telcordia GR-253-CORE defines an "Continuous Add" Pointer Adjustment, as the "Continuous" Pointer Adjustment pattern, with an additional pointer ...

Page 119

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 Telcordia GR-253-CORE defines a "Continuous Cancel" Pointer Adjustment, as the "Continuous" Pointer Adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in Figure 63. ...

Page 120

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 8.7.2 Wander Measurement Test Results Wander Measurement test results will be provided in the next revision of the LIU Data Sheet. 8.8 Designing with the LIU In this section, we ...

Page 121

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 Using a particular clock edge within the "gapped" clock signal (from the Mapper IC) to sample and latch the value of each DS3 data-bit that is output from the ...

Page 122

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER c. Configure each of the channels within the LIU to operate in the SONET De-Sync Mode The user can accomplish this by executing of the following step. If the LIU ...

Page 123

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 ABLE ITTER TTENUATOR Unused R/O R/O R OTES 1. The ability to ...

Page 124

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER During this effort, we learned the following. 1. This "DS3 Clock" and "Data" signal, which is output from the Mapper IC consists of two major "repeating" patterns (which we will ...

Page 125

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 Figure 67 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN IGURE LLUSTRATION OF ROCEDURE WHICH IS USED TO ...

Page 126

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER Figure 69 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN IGURE LLUSTRATION OF ROCEDURE WHICH IS USED TO Repeats ...

Page 127

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 output a DS3 line signal (to the DS3 facility) that complies with the "Category I Intrinsic Jitter Requirements - per Telcordia GR-253-CORE (for DS3 applications). This scheme is illustrated ...

Page 128

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 50: M ABLE EASURED DS3 PPM O ( W&G ANT-20SE) FFSET PER 0 ppm +10 ppm +20 ppm +30 ppm +40 ppm +99 ppm N : The APS Completion ...

Page 129

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0 ABLE ITTER TTENUATOR Unused R/O R/O R REFERENCES 1. TEST REPORT - AUTOMATIC PROTECTION ...

Page 130

XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 9.0 ELECTRICAL CHARACTERISTICS P SYMBOL ARAMETER V Supply Voltage DD V Input Voltage at any Pin IN I Input current at any pin IN S Storage Temperature TEMP A Ambient ...

Page 131

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 T ABLE SYMBOL P STS1 Power Consumption CC_STS1 P STS1 Power Consumption with Jitter Attenuator Enabled CC_STS1JA V 2 Input Low Voltage Input High Voltage IH ...

Page 132

... XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER P N ART UMBER XRT75R12DIB PACKAGE DIMENSIONS - ORDERING INFORMATION P ACKAGE 420 TBGA 420 Tape Ball Grid Array ( mm, TBGA) Rev. 1. (A1 corner feature is mfger option) INCHES MILLIMETERS SYMBOL MIN MAX MIN A 0.051 0.067 1 ...

Page 133

... EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...