AGL030V2-CSG81 Actel, AGL030V2-CSG81 Datasheet - Page 105
AGL030V2-CSG81
Manufacturer Part Number
AGL030V2-CSG81
Description
FPGA - Field Programmable Gate Array 30K System Gates IGLOO
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL030V2-CSG81
Processor Series
AGL030
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
66
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
30 K
Package / Case
CSP-81
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL030V2-CSG81
Manufacturer:
NVIDIA
Quantity:
7
Part Number:
AGL030V2-CSG81
Manufacturer:
ACTEL/爱特
Quantity:
20 000
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Table 2-158 • Output Data Register Propagation Delays
Table 2-159 • Output Data Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Timing Characteristics
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
1.5 V DC Core Voltage
1.2 V DC Core Voltage
J
J
= 70°C, Worst-Case VCC = 1.425 V
= 70°C, Worst-Case VCC = 1.14 V
Description
Description
R ev i si o n 1 8
Table 2-6 on page 2-7
Table 2-7 on page 2-7
IGLOO Low Power Flash FPGAs
for derating values.
for derating values.
1.00
0.51
0.70
0.00
1.34
1.34
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
1.52
1.15
0.00
1.96
1.96
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std.
0.00
Std.
0.00
1.11
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 91
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