AGL030V2-CSG81 Actel, AGL030V2-CSG81 Datasheet - Page 18

• Manufacturer Part Number: AGL030V2-CSG81
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL030V2-CSG81

• Processor Series: AGL030
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 66
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 30 K
• Package / Case: CSP-81
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO DC and Switching Characteristics
Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
2- 4
Deactivation trip point:
V
V
Activation trip point:
a
d
= 0.85 V ± 0.25 V
= 0.75 V ± 0.25 V
VCC = 1.575 V
VCC = 1.425 V
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up
behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels (see
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes low and/or the
output clock is lost. Refer to the Brownout Voltage section in the "Power-Up/-Down Behavior of Low
Power Flash Devices" chapter of the
information on clock and lock recovery.
Internal Power-Up Activation Sequence
To make sure the transition from input buffers to output buffers is clean, ensure that there is no path
longer than 100 ns from input buffer to output buffer in your design.
VCC
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
Region 1: I/O Buffers are OFF
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
Deactivation trip point:
Activation trip point:
V
V
a
d
= 0.9 V ± 0.3 V
= 0.8 V ± 0.3 V
Figure 2-1
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
buffers do not meet VOH / VOL levels.
and
meet VIH / VIL levels, and output
same reason, input buffers do not
is below specification. For the
Figure 2-2 on page 2-5
but slower because VCCI
(except differential
(except differential inputs)
ProASIC
I/Os are functional
I/Os are functional
R ev isio n 1 8
buffers are ON.
buffers are ON.
Region 4: I/O
Region 4: I/O
Min VCCI datasheet specification
standard; i.e., 1.425 V or 1.7 V
®
3
voltage at a selected I/O
and
or 2.3 V or 3.0 V
ProASIC3E
for more details).
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
speed, VIH / VIL, VOH / VOL,
etc.
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
FPGA fabric user’s guides for
VCCI