AGL030V2-CSG81 Actel, AGL030V2-CSG81 Datasheet - Page 229

• Manufacturer Part Number: AGL030V2-CSG81
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL030V2-CSG81

• Processor Series: AGL030
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 66
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 30 K
• Package / Case: CSP-81
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
Revision 10 (Aug 2008) 3.0 V LVCMOS wide range support data was added to
DC and Switching
Characteristics
Advance v0.4
Revision 9 (Jul 2008)
Product Brief v1.1
DC and Switching
Characteristics
Advance v0.3
Revision 8 (Jun 2008)
DC and Switching
Characteristics
Advance v0.2
Recommended Operating Conditions
3.3 V LVCMOS wide range support data was added to
Maximum and Minimum DC Input and Output Levels Applicable to Commercial
and Industrial Conditions—Software Default Settings
Maximum and Minimum DC Input and Output Levels Applicable to Commercial
and Industrial Conditions—Software Default
3.3 V LVCMOS wide range support data was added to
Maximum and Minimum DC Input
3.3 V LVCMOS wide range support text was added to
Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide
Table 2-49 · Minimum and Maximum DC Input and Output Levels for LVCMOS
3.3 V Wide Range
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
Tables have been updated to reflect default values in the software. The default
I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V
I/O set.
DDR Tables have two additional data points added to reflect both edges for Input
DDR setup and hold time.
The power data table has been updated to match SmartPower data rather then
simulation values.
AGL015 global clock delays have been added.
Table 2-1 • Absolute Maximum Ratings
VMV parameters in one row. The word "output" from the parameter description
for VCCI and VMV, and table note 3 was added.
Table 2-2 • Recommended Operating Conditions
references to tables notes 4, 6, 7, and 8. VMV was added to the VCCI parameter
row, and table note 9 was added.
In
Temperature1, the maximum operating junction temperature was changed from
110° to 100°.
VMV was removed from
table title was modified to remove "as measured on quiet I/Os." Table note 2 was
revised to remove "estimated SSO density over cycles." Table note 3 was
revised to remove "refers only to overshoot/undershoot limits for simultaneous
switching I/Os.
The
Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage
Levels
Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating
"PLL Behavior at Brownout Condition" section
is new.
"
is new.
Table 2-4 • Overshoot and Undershoot Limits
R ev i si o n 1 8
Levels.
Changes
4
.
was updated to combine the VCCI and
Settings.
is new.
to
Table 2-49 · Minimum and
4
Table 2-24 • Summary of
Table 2-27 • Summary of
Table 2-26 • Summary of
was updated to add
IGLOO Low Power Flash FPGAs
Range.
Table 2-2 •
1. The
2-24
Page
2-26
2-27
2-39
2-39
N/A
N/A
N/A
2-2
2-1
2-2
2-2
2-3
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2-5
to
4 -3