AGL030V2-CSG81 Actel, AGL030V2-CSG81 Datasheet - Page 230

• Manufacturer Part Number: AGL030V2-CSG81
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL030V2-CSG81

• Processor Series: AGL030
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 66
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 30 K
• Package / Case: CSP-81
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4- 4
Revision
Revision 8 (cont’d)
Revision 7 (Jun 2008)
Packaging v1.5
Revision 6 (Jun 2008)
Packaging v1.4
Revision 5 (Mar 2008)
Packaging v1.3
EQ 2
end result changed.
The table notes for
IGLOO Flash*Freeze
Characteristics, IGLOO Sleep
Current (IDD) Characteristics, IGLOO Shutdown Mode
VMV and include PDC6 and PDC7. VCCI and VJTAG were removed from the
statement about IDD in the table note for
(IDD) Characteristics, IGLOO Shutdown
Note 2 of
Mode1
and PDC7.
Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings,
Software
Default I/O Software
Power (per pin) – Default I/O Software Settings
to PDC6 and PDC3 to PDC7. The table notes were updated to reflect that power
was measured on VCCI.
In
Consumption in IGLOO
Static to Dynamic.
Table 2-19 • Different Components Contributing to the Static Power
Consumption in IGLOO Devices
Contributing to the Static Power Consumption in IGLOO Device
add PDC6 and PDC7, and to change the definition for PDC5 to bank quiescent
power. Subtitles were added to indicate type of devices and core supply voltage.
The
calculation of P
Footnote 1
Contribution equation was changed from: P
P
The
addition, note 1 was changed from top view to bottom view, and note 2 is new.
This document was divided into two sections and given a version number,
starting at v1.0. The first section of the document includes features, benefits,
ordering information, and temperature and speed grade offerings. The second
section is a device family overview.
Pin numbers were added to the
added below the diagram.
The
PLL
Table 2-18 • Different Components Contributing to Dynamic Power
"Total Static Power Consumption—P
"196-Pin CSP"
"132-Pin QFN"
= P
was updated. The temperature was changed to 100°C, and therefore the
was updated to include VCCPLL. Note 4 was updated to include PDC6
DC4
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O
Settings,
Table 2-11 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze
was updated to include information about PAC13. The PLL
+ P
STAT
AC13
Table 2-14 • Summary of I/O Input Buffer Power (per pin) –
, including PDC6 and PDC7.
package and pin table was added for AGL250.
Table 2-8 • Quiescent Supply Current (IDD) Characteristics,
* F
package diagram was updated to include D1 to D4. In
Settings, and
Mode*,
CLKOUT
Devices, the description for PAC13 was changed from
.
R ev isio n 1 8
Table 2-9 • Quiescent Supply Current (IDD)
Mode*, and
"68-Pin QFN"
Changes
Table 2-15 • Summary of I/O Output Buffer
and
Mode.
STAT
Table 2-10 • Quiescent Supply Current
Table 2-21 • Different Components
PLL
" section
Table 2-10 • Quiescent Supply
1
= P
package diagram. Note 2 was
were updated to change PDC2
AC13
was updated to revise the
were updated to remove
+ P
AC14
were updated to
* F
CLKOUT
to
through
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