AGL030V2-CSG81 Actel, AGL030V2-CSG81 Datasheet - Page 34

• Manufacturer Part Number: AGL030V2-CSG81
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL030V2-CSG81

• Processor Series: AGL030
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 66
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 30 K
• Package / Case: CSP-81
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO DC and Switching Characteristics
User I/O Characteristics
Figure 2-3 • Timing Model
2- 20
I/O Banks only)
to Advanced
(Applicable
LVPECL
(Applicable for
Advanced I/O
t
PY
Banks only)
= 0.87 ns (Advanced I/O Banks)
Clock
M-LVDS
Input LVTTL
BLVDS,
LVDS,
Timing Model
Operating Conditions: Std. Speed, Commercial Temperature Range (T
VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
t
PY
(Non-Registered)
(Registered)
= 1.20 ns
I/O Module
I/O Module
t
t
t
PY
ICLKQ
ISUD
= 1.35 ns
= 0.47 ns
= 0.43 ns
D
Q
Register Cell
t
t
CLKQ
SUD
D
= 0.82 ns
= 0.90 ns
Combinational Cell
Q
(Advanced I/O Banks)
Combinational Cell
t
PD
Combinational Cell
t
PD
Clock
Input LVTTL
t
PY
= 1.80 ns
t
= 1.22 ns
PD
= 0.87 ns
= 0.92 ns
Combinational Cell
Combinational Cell
Y
Y
t
PD
t
PD
Y
= 1.49 ns
= 0.86 ns
R ev i sio n 1 8
Register Cell
Combinational Cell
t
t
CLKQ
SUD
D
t
PD
Y
Y
= 0.82 ns
(Non-Registered)
= 0.90 ns
= 1.20 ns
(Advanced I/O Banks)
t
Q
I/O Module
DP
Clock
t
Input LVTTL
PY
= 3.05 ns (Advanced I/O Banks)
(Non-Registered)
(Non-Registered)
t
t
DP
I/O Module
I/O Module
DP
= 0.87 ns
Y
= 4.42 ns (Advanced I/O Banks)
= 4.12 ns (Advanced I/O Banks)
(Non-Registered)
I/O Module
t
DP
LVTTL Output drive strength = 12 mA
= 1.72 ns
t
t
D
OCLKQ
OSUD
(Registered)
I/O Module
LVTTL Output drive strength = 8 mA
LVCMOS 1.5 V Output drive strength = 4 mA
High slew rate
Q
= 0.52 ns
= 1.02 ns
t
(Advanced I/O Banks)
DP
High slew rate
= 3.05 ns
LVPECL (Applicable to
Advanced I/O Banks Only)L
J
= 70°C), Worst-Case
High slew rate
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate