AGL030V2-CSG81 Actel, AGL030V2-CSG81 Datasheet - Page 93

• Manufacturer Part Number: AGL030V2-CSG81
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL030V2-CSG81

• Processor Series: AGL030
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 66
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 30 K
• Package / Case: CSP-81
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-140 • Minimum and Maximum DC Input and Output Levels
Figure 2-12 • AC Loading
Table 2-141 • AC Waveforms, Measuring Points, and Capacitive Loads
3.3 V PCI/PCI-X
Drive Strength
Per PCI
specification
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Input Low (V)
0
*
Measuring point = Vtrip. See
Test Point
Datapath
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path
characterization are described in
AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is
described in
Applicable to Advanced and Standard Plus I/Os
R = 25
Min.
V
VIL
Table
Max.
R to VCCI for t
R to GND for t
V
Table 2-28 on page 2-28
2-141.
Input High (V)
Min.
V
VIH
3.3
DP
Max.
DP
Figure
V
(R)
(F)
2-12.
Per PCI curves
Max.
VOL
Enable Path
for a complete table of trip points.
V
Test Point
R ev i si o n 1 8
0.285 * VCCI for t
0.615 * VCCI for t
Measuring Point* (V)
VOH
Min.
R = 1 k
V
mA mA
I
OL
I
10 pF for t
R to VCCI for t
R to GND for t
OH
5 pF for t
DP(R)
DP(F)
Max.
I
mA
OSH
HZ
ZH
IGLOO Low Power Flash FPGAs
1
/ t
/ t
HZ
LZ
LZ
ZHS
/ t
/ t
C
Max.
mA
I
OSL
LOAD
ZL
ZH
/ t
ZL
1
10
/ t
/ t
ZLS
/ t
ZHS
(pF)
ZLS
µA
10
I
IL
2
µA
I
10
2- 79
IH
2