AGL030V2-CSG81 Actel, AGL030V2-CSG81 Datasheet - Page 95
AGL030V2-CSG81
Manufacturer Part Number
AGL030V2-CSG81
Description
FPGA - Field Programmable Gate Array 30K System Gates IGLOO
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL030V2-CSG81
Processor Series
AGL030
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
66
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
30 K
Package / Case
CSP-81
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL030V2-CSG81
Manufacturer:
NVIDIA
Quantity:
7
Part Number:
AGL030V2-CSG81
Manufacturer:
ACTEL/爱特
Quantity:
20 000
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Figure 2-13 • LVDS Circuit Diagram and Board-Level Implementation
OUTBUF_LVDS
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the
user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, IGLOO also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
FPGA
P
N
Bourns Part Number: CAT16-LV4F12
165 Ω
165 Ω
140 Ω
R ev i si o n 1 8
Z
Z
0
0
= 50 Ω
= 50 Ω
100 Ω
N
P
IGLOO Low Power Flash FPGAs
FPGA
+
–
INBUF_LVDS
Figure
2-13. The
2- 81
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