A3P250L-VQG100 Actel, A3P250L-VQG100 Datasheet - Page 118
A3P250L-VQG100
Manufacturer Part Number
A3P250L-VQG100
Description
FPGA - Field Programmable Gate Array 2.5K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P250L-VQG100
Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
68
Data Ram Size
36864
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P250L-VQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P250L-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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ProASIC3L DC and Switching Characteristics
Table 2-182 • Input Data Register Propagation Delays
Table 2-183 • Input Data Register Propagation Delays
2- 10 4
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
Timing Characteristics
Commercial-Case Conditions: T
Commercial-Case Conditions: T
1.5 V DC Core Voltage
1.2 V DC Core Voltage
J
J
Description
Description
= 70°C, Worst-Case VCC = 1.425 V
= 70°C, Worst-Case VCC = 1.14 V
R e visio n 9
Table 2-6 on page 2-7
Table 2-6 on page 2-7
for derating values.
for derating values.
0.24 0.29
0.27 0.31
0.00 0.00
0.38 0.45
0.00 0.00
0.46 0.54
0.46 0.54
0.00 0.00
0.23 0.27
0.00 0.00
0.23 0.27
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
0.32 0.37
0.35 0.41
0.00 0.00
0.50 0.58
0.00 0.00
0.60 0.71
0.60 0.71
0.00 0.00
0.30 0.35
0.00 0.00
0.30 0.35
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
–1
–1
Std. Units
Std. Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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