LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 133
LFXP2-8E-5FTN256I
Manufacturer Part Number
LFXP2-8E-5FTN256I
Description
FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5FTN256I
Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
226304
Number Of I /o
201
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package
256FTBGA
Family Name
LatticeXP2
Device Logic Units
8000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
201
Ram Bits
226304
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5FTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LatticeXP2 sysCLOCK PLL
Lattice Semiconductor
Design and Usage Guide
Figure 9-8. IPexpress Main Window
Configuration Tab
The Configuration Tab lists all user accessible attributes with default values set. Upon completion, clicking Gener-
ate will generate source and constraint files. Users may choose to use the .lpc file to load parameters.
Configuration Modes
There are two modes that can be used to configure the PLL in the Configuration Tab, Frequency Mode and Divider
Mode.
Frequency Mode: In this mode, the user enters input and output clock frequencies and the software calculates the
divider settings. If the output frequency entered is not achievable the nearest frequency will be displayed in the
‘Actual’ text box. After input and output frequencies are entered, clicking the Calculate button will display the
divider values.
Divider Mode: In this mode, the user sets the divider settings with input frequency. Users must choose the CLKOP
Divider value to maximize the f
and achieve optimum PLL performance. After input frequency and divider set-
VCO
tings are set, clicking the Calculate button will display the frequencies. Figure 9-9 shows the Configuration Tab.
9-11
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