LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 214
LFXP2-8E-5FTN256I
Manufacturer Part Number
LFXP2-8E-5FTN256I
Description
FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5FTN256I
Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
226304
Number Of I /o
201
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package
256FTBGA
Family Name
LatticeXP2
Device Logic Units
8000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
201
Ram Bits
226304
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5FTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 11-12. IDDRMX1A Waveform
IDDRMFX1A
With the IDDRMX1A, the data can enter the FPGA at either the positive or negative edge of the SCLK depending
on the state of the DDRCLKPOL signal. The IDDRMFX1A module includes an additional clock transfer stage that
ensures that the data is transferred at a known edge of the system clock.
Figure 11-13. IDDRMFX1A Symbol
Table 11-4 provides a description of all I/O ports associated with the IDDRMFX1A primitive.
ECLK( DQS shifted 90 deg)
DDR DATA at IDDRMX1A
Case 1: DDRCLKPOL = 0
Case 2: DDRCLKPOL = 1
DDR DATA at I/O
DQS at I/O
SCLK
SCLK
QA
QB
QA
QB
B
C
A
P0
P0
XX
XX
XX
XX
XX
XX
P0
N0
N0
ECLK
RST
CLK1
CLK2
CE
DDRCLKPOL
D
P0
N0
P1
P1
IDDRMFX1A
11-10
P0
N0
P0
N0
P1
N1
N1
N1
P1
P2
P2
QA
QB
LatticeXP2 High-Speed I/O Interface
P1
N1
P1
N1
P2
N2
N2
N2
P2
P3
P3
P2
N2
P2
N2
P3
N3
N3
P3
N3
P4
P4
P3
N3
P3
N3
P4
N4
N4
P4
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