A3P1000L-FGG256 Actel, A3P1000L-FGG256 Datasheet - Page 149
A3P1000L-FGG256
Manufacturer Part Number
A3P1000L-FGG256
Description
FPGA - Field Programmable Gate Array 1M SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P1000L-FGG256
Processor Series
A3P1000
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
177
Data Ram Size
147456
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
1 M
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P1000L-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P1000L-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P1000L-FGG256I
Manufacturer:
ACTEL
Quantity:
20 000
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Table 2-209 • RAM4K9 – Applies to 1.2 V DC Core Voltage
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
WRO
CCKH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (flow-through, WMODE = 1)
Clock High to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write on same
address
Address collision clk-to-clk delay for reliable write access after write/read on same
address
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum frequency
Commercial-Case Conditions: T
J
Description
= 70°C, Worst-Case VCC = 1.14 V
R e v i s i o n 9
Table 2-6 on page 2-7
ProASIC3L Low Power Flash FPGAs
for derating values.
0.33 0.39
0.00 0.00
0.19 0.22
0.13 0.15
0.31 0.36
0.02 0.03
0.24 0.29
0.00 0.00
2.38 2.80
3.14 3.69
1.19 1.40
TBD TBD
TBD TBD
1.23 1.45
1.23 1.45
0.38 0.45
2.00 2.35
0.63 0.72
5.75 6.61
174 151
–1
Std.
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 135
s
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