AGLN010V5-UCG36 Actel, AGLN010V5-UCG36 Datasheet - Page 34
AGLN010V5-UCG36
Manufacturer Part Number
AGLN010V5-UCG36
Description
FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN010V5-UCG36
Processor Series
AGLN010
Core
IP Core
Number Of Macrocells
86
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
23
Supply Voltage (max)
1.5 V
Supply Current
3 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
10 K
Package / Case
uCSP-36
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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IGLOO nano DC and Switching Characteristics
Table 2-23 • Summary of AC Measuring Points
Table 2-24 • I/O AC Parameter Definitions
2- 20
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
Parameter
t
t
t
t
t
t
t
t
t
t
t
DP
PY
DOUT
EOUT
DIN
HZ
ZH
LZ
ZL
ZHS
ZLS
Summary of I/O Timing Characteristics – Default I/O Software Settings
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—HIGH to Z
Enable to Pad delay through the Output Buffer—Z to HIGH
Enable to Pad delay through the Output Buffer—LOW to Z
Enable to Pad delay through the Output Buffer—Z to LOW
Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH
Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW
Parameter Definition
R ev i sio n 1 1
Measuring Trip Point (Vtrip)
0.60 V
0.60 V
0.90 V
0.75 V
1.4 V
1.4 V
1.2 V
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