A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 220

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4 - 2
Revision
Revision 6 (cont’d)
Revision 5 (Jul 2008)
Product Brief v1.1
DC and Switching
Characteristics
Advance v0.4
Revision 4 (Jun 2008)
DC and Switching
Characteristics
Advance v0.3
Table 2-206 • ProASIC3LP CCC/PLL Specification
1.2 V and
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
Tables have been updated to include the LVCMOS 1.2 V I/O set.
DDR Tables have two additional data points added to reflect both edges for Input
DDR setup and hold time.
Power data table has been updated to match SmartPower data rather then
simulation values.
Table 2-1 • Absolute Maximum Ratings
parameter row and to remove the word "output" from the parameter description
for VCCI. Table note 3 was added.
Table 2-2 • Recommended Operating Conditions
references and rearrange the order of notes. VMV was added to the VCCI
parameter row. A new row was added for VCC, 1.5 V DC core supply voltage.
The table note stating that 1.5 V data will be released at a later date is new. The
table note on VMV pins is new.
Table 2-4 • Overshoot and Undershoot Limits
"as measured on quiet I/Os." Table note 2 was revised to remove "estimated SSO
density over cycles." Table note 3 was revised to remove "refers only to
overshoot/undershoot limits for simultaneous switching I/Os.
EQ 2
end result changed.
The table notes for
ProASIC3L Flash*Freeze Mode*
Characteristics, ProASIC3L Sleep Mode (VCC = 0 V)*
VMV and include P
Current (I
include VJTAG.
Table 2-9 • Quiescent Supply Current (I
(VCC, VCCI = 0 V)
Note 2 of
Flash*Freeze Mode1
include P
Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings
Default I/O Software Settings
P
The subtitle of the table was changed from "Applicable to Advanced I/O Banks" to
"Applicable to Pro I/O Banks."
The word "input" in the titles of
(per pin) – Default I/O Software Settings
Output Buffer Power (per pin) – Default I/O Software Settings
"output."
DC7
. The table notes were updated to reflect that power was measured on V
was updated. The temperature was changed to 100°C, and therefore the
through
DC6
DD
Table 2-207 • ProASIC3LP CCC/PLL Specification
) Characteristics, ProASIC3L Flash*Freeze Mode*
Table 2-10 • Quiescent Supply Current (I
and P
Table 2-16 • Summary of I/O Output Buffer Power (per pin) –
DC6
is new.
DC7
Table 2-7 • Quiescent Supply Current (I
was updated to include VCCPLL. Note 4 was updated to
.
and P
DC7
1
were updated to change P
Table 2-14 • Summary of I/O Output Buffer Power
. The table note for
and
R e vi s i o n 9
Changes
Table 2-8 • Quiescent Supply Current (I
was updated to add VMV to the VCCI
DD
1
) Characteristics, Shutdown Mode
and
1
. The title was revised to remove
1
Table 2-15 • Summary of I/O
was updated to add table note
was updated for core voltage
Table 2-7 • Quiescent Supply
were updated to remove
DC2
DD
"
to P
for 1.5 V is new.
DD
), No ProASIC3L
1
, was changed to
) Characteristics,
was updated to
DC6
and P
DC3
CCI
DD
to
)
.
2-11,
through
2-126,
2-127
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2-12
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