A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 28

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3L DC and Switching Characteristics
Table 2-18 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at
Table 2-19 • Different Components Contributing to the Static Power Consumption in ProASIC3L Devices
2- 14
Parameter
P
P
P
P
P
P
P
P
P
P
P
P
P
*
Parameter
P
P
P
P
P
P
P
*
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
DC1
DC2
DC3
DC4
DC5
DC6
DC7
For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet
calculator or SmartPower tool in Libero IDE.
For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet
calculator or SmartPower tool in Libero IDE.
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
Clock contribution of a VersaTile used as a sequential
module
First contribution of a VersaTile used as a sequential
module
Second contribution of a VersaTile used as a sequential
module
Contribution of a VersaTile used as a combinatorial
Module
Average contribution of a routing net
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read
operation
Average contribution of a RAM block during a write
operation
Dynamic contribution for PLL
1.5 V VCC
Array static power in Active mode
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
Static PLL contribution at 1.2 V core (operating mode
only)
Static PLL contribution at 1.5 V core (operating mode
only)
Bank quiescent power (VCCI-dependent)
I/O input pin static power (standard-dependent)
I/O output pin static power (standard-dependent)
Definition
Definition
R e visio n 9
A3PE3000L A3P1000L A3P600L A3P250L
A3PE3000L A3P1000L A3P600L A3P250L
Device Specific Dynamic Power (µW/MHz)
See
Device Specific Dynamic Power (µW)
See
See
19.7
4.16
0.88
See
See
page
Table 2-7 on page
See
Table 2-14 on page 2-11
See
See
Table 2-11 on page 2-9
Table 2-14 on page 2-11
Table 2-13 on page
Table 2-16 on page
Table 2-11 on page
2-7,
Table 2-13 on page
Table 2-16 on page
Table 2-10 on page
Table 2-8 on page
Table 2-7 on page
Table 2-10 on page
14.50
2.48
1.42 mW
2.55 mW
25.00
30.00
0.12
0.07
0.29
0.29
0.70
2.60
2-7,
12.80
0.81
1.85
2-9. through
2-10.
2-12.
Table 2-8 on
2-10.
2-12.
2-7.
2-7.
2-8.
through
through
through
2-8.
11.00
1.58