A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 89

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-120 • Minimum and Maximum DC Input and Output Levels
Figure 2-12 • AC Loading
Table 2-121 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-122 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage
3.3 V PCI/PCI-X
Drive Strength
Per PCI specification
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Input Low (V)
0
*
Speed Grade
Std.
–1
Note:
Measuring point = V
Test Point
For specific junction temperature and voltage supply levels, refer to
Datapath
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
AC loadings are defined per the PCI/PCI-X specifications for the database; Actel loadings for enable path
characterization are described in
AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is
described in
Timing Characteristics
Commercial-Case Conditions: T
Applicable to Pro I/O Banks
R = 25
1.5 V DC Core Voltage
t
DOUT
0.59
0.50
trip.
Min.
2.52
2.15
See
Table
t
V
DP
R to VCCI for t
R to GND for t
VIL
Table 2-26 on page 2-25
2-121.
Max.
0.04
0.03
t
DIN
V
Input High (V)
2.47
2.10
t
Min.
3.3
PY
V
DP
DP
Figure
VIH
(R)
(F)
J
t
3.33
2.84
PYS
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Max.
V
2-12.
Enable Path
Test Point
for a complete table of trip points.
t
0.38
0.33
EOUT
Per PCI curves
R e v i s i o n 9
Max.
VOL
V
0.285 * VCCI for t
0.615 * VCCI for t
Measuring Point* (V)
R = 1 k
2.57
2.19
t
ZL
VOH
Min.
V
1.80
1.53
t
ZH
Table 2-6 on page 2-7
mA mA
I
OL
10 pF for t
R to VCCI for t
R to GND for t
5 pF for t
I
DP(R)
DP(F)
OH
2.95
2.51
t
LZ
ProASIC3L Low Power Flash FPGAs
Max.
HZ
mA
I
ZH
OSL
3.25
2.77
t
HZ
/ t
/ t
1
HZ
LZ
LZ
ZHS
/ t
/ t
t
4.58
3.90
ZLS
for derating values.
C
ZH
/ t
ZL
LOAD
Max.
I
mA
ZL
OSH
/ t
/ t
10
ZLS
/ t
1
ZHS
t
3.81
3.24
(pF)
ZHS
ZLS
µA
10
I
IL
Units
2
ns
ns
µA
2- 75
I
10
IH
2