A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 95

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-136 • Minimum and Maximum DC Input and Output Levels
Figure 2-15 • AC Loading
Table 2-137 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-138 • 3.3 V GTL+ – Applies to 1.5 V DC Core Voltage
Table 2-139 • 3.3 V GTL+ – Applies to 1.2 V DC Core Voltage
3.3 V GTL+
Drive
Strength
35 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.1
*
Speed
Grade
Std.
–1
Note:
Speed
Grade
Std.
–1
Note:
Measuring point = V
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The V
Timing Characteristics
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 1.0 V
Applicable to Pro I/O Banks
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 1.0 V
Applicable to Pro I/O Banks
t
t
Min.
–0.3
DOUT
0.59
0.50
DOUT
0.77
0.66
V
Input High (V)
VIL
trip
VREF – 0.1 VREF + 0.1
VREF + 0.1
. See
1.85
1.57
1.85
1.57
Max.
t
t
DP
DP
V
Table 2-15 on page 2-12
0.04
0.03
0.05
0.04
t
t
DIN
DIN
Min.
V
2.12
1.80
2.12
1.80
Measuring
t
t
Point* (V)
PY
PY
VIH
Test Point
1.0
J
J
= 70°C, Worst-Case VCC = 1.425 V,
= 70°C, Worst-Case VCC = 1.14 V,
Max.
t
t
3.6
0.38
0.33
0.50
0.43
EOUT
EOUT
V
GTL+
for a complete table of trip points.
R e v i s i o n 9
Max.
VOL
VREF (typ.) (V)
0.6
V
1.88
1.60
1.88
1.60
V
t
t
TT
ZL
ZL
25
10 pF
1.0
VOH
Min.
1.85
1.57
1.85
1.57
t
t
V
–
ZH
ZH
CCI
Table 2-6 on page 2-7
Table 2-6 on page 2-7
mA mA
pin should be connected to 3.3 V
I
35 35
OL
t
t
LZ
LZ
VTT (typ.) (V)
I
OH
ProASIC3L Low Power Flash FPGAs
t
t
HZ
HZ
1.5
Max.
mA
I
268
OSL
3.90
3.31
3.90
3.31
t
t
1
ZLS
ZLS
for derating values.
for derating values.
Max.
I
mA
181
OSH
t
3.86
3.29
t
3.86
3.29
ZHS
ZHS
C
1
LOAD
10
µA
I
10
(pF)
IL
Units
Units
2
ns
ns
ns
ns
µA
2- 81
I
10
IH
2