LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 195
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 10-50. READ_ID Waveform
WRITE_EN (ACh)
The WRITE_EN command enables the TAG memory for programming. If the WRITE_EN command has not been
shifted into the device first, the PROGRAM_TAG, ERASE_TAG and STATUS commands do not take effect. This is
to prevent the TAG memory from erroneous erase or program.
The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any
extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is
driven from low to high, a minimum of three clocks are required to complete the execution of the command.
The effect of this command is terminated by the WRITE_DIS command.
Figure 10-51. WRITE_EN Waveform
WRITE_DIS (78h)
The WRITE_DIS command disables the TAG memory for programming. It does not nullify the READ_TAG and
READ_ID commands.
The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any
extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is
driven from low to high, a minimum of three clocks are required to complete the execution of the command.
CS
CLK
SI
SO
CS
CLK
SI
SO
8 Bits READ_ID
Command
Shifting Clocks
8 Command
3 Clocks To Initiate And Complete
24 Bits Dummy
HI-Z
Optional Extra Clocks
10-45
HIGH IMPEDANCE
0 1 2
32 Bits JTAG IDCODE
LatticeXP2 Memory Usage Guide
31
HI-Z
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