AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 238
AFS600-FGG256
Manufacturer Part Number
AFS600-FGG256
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS600-FGG256
Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
119
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number:
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135
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AFS600-FGG256
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
AFS600-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AFS600-FGG256K
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Device Architecture
Figure 2-141 • Input DDR Timing Diagram
Table 2-177 • Input DDR Propagation Delays
2- 22 2
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
CLK
Data
CLR
Out_QF
Out_QR
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
For the derating values at specific junction temperature and voltage supply levels, refer to
page
Commercial Temperature Range Conditions: T
3-9.
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
Data Hold for Input DDR
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
Timing Characteristics
t
t
1
DDRICLR2Q2
DDRICLR2Q1
t
DDRIREMCLR
2
3
Description
t
DDRICLKQ1
4
2
R e visio n 1
3
J
5
= 70°C, Worst-Case VCC = 1.425 V
t
DDRICLKQ2
t
DDRISUD
6
4
1,404
0.39
0.57
0.22
0.22
0.36
0.32
0.27
0.28
0.00
0.46
0.00
5
–2
7
1,048
0.44
0.31
0.32
0.00
0.65
0.25
0.25
0.41
0.37
0.53
0.00
–1
t
DDRIHD
t
DDRIRECCLR
6
8
7
1,232
0.52
0.37
0.38
0.00
0.76
0.62
0.00
0.30
0.30
0.48
0.43
Std.
Table 3-7 on
Units
9
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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