AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 240
AFS600-FGG256
Manufacturer Part Number
AFS600-FGG256
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS600-FGG256
Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
119
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
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Quantity
Price
Company:
Part Number:
AFS600-FGG256
Manufacturer:
Actel
Quantity:
135
Part Number:
AFS600-FGG256
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
AFS600-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AFS600-FGG256K
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Device Architecture
Figure 2-143 • Output DDR Timing Diagram
Table 2-179 • Output DDR Propagation Delays
2- 22 4
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
Data_F
Data_R
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
CLK
CLR
Out
DDOMAX
For the derating values at specific junction temperature and voltage supply levels, refer to
page
6
Commercial Temperature Range Conditions: T
3-9.
t
DDROCLR2Q
1
Timing Characteristics
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
t
DDROREMCLR
t
DDROSUD1
7
2
t
t
DDROCLKQ
DDROHD1
7
Description
t
DDROSUD2
8
3
2
R e visio n 1
t
DDROHD2
J
= 70°C, Worst-Case VCC = 1.425 V
8
4
9
3
1,048
t
0.70
0.38
0.38
0.00
0.80
0.00
0.22
0.22
0.36
0.32
0.00
DDRORECCLR
–2
9
1,232
0.80
0.43
0.43
0.00
0.00
0.91
0.00
0.25
0.25
0.41
0.37
10
4
–1
5
1,404
0.94
0.51
0.51
0.00
0.00
1.07
0.00
0.30
0.30
0.48
0.43
Std.
Table 3-7 on
10
Units
11
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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