AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 34
AFS600-FGG256
Manufacturer Part Number
AFS600-FGG256
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS600-FGG256
Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
119
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AFS600-FGG256
Manufacturer:
Actel
Quantity:
135
Part Number:
AFS600-FGG256
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
AFS600-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AFS600-FGG256K
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Device Architecture
Table 2-7 • AFS250 Global Resource Timing
Table 2-8 • AFS090 Global Resource Timing
2- 18
Parameter
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a
3. For the derating values at specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a
3. For the derating values at specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKSW
RCKL
RCKH
RCKSW
RMAX
RMAX
located in a lightly loaded row (single element is connected to the global net).
fully loaded row (all available flip-flops are connected to the global net in the row).
located in a lightly loaded row (single element is connected to the global net).
fully loaded row (all available flip-flops are connected to the global net in the row).
Commercial Temperature Range Conditions: T
Commercial Temperature Range Conditions: T
Input Low Delay for Global Clock
Input High Delay for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input Low Delay for Global Clock
Input High Delay for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Description
Description
Min.
0.89
0.88
R e visio n 1
Min.
0.84
0.83
1
J
J
1
–2
–2
= 70°C, Worst-Case VCC = 1.425 V
= 70°C, Worst-Case VCC = 1.425 V
Max.
1.12
1.14
0.26
Max.
1.07
1.10
0.27
2
2
Min.
1.02
1.00
Min.
0.96
0.95
1
–1
1
–1
Max.
1.27
1.30
0.30
Max.
1.21
1.25
0.30
Table 3-7 on page
Table 3-7 on page
2
2
Min.
1.20
1.17
Min.
1.13
1.12
1
Std.
1
Std.
Max.
Max.
1.50
1.53
0.35
1.43
1.47
0.36
3-9.
3-9.
2
2
Units
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
s
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