LFXP2-5E-5QN208C Lattice, LFXP2-5E-5QN208C Datasheet - Page 16

FPGA - Field Programmable Gate Array 5K LUTs 146I/O Inst- on DSP 1.2V -5 Spd

LFXP2-5E-5QN208C

Manufacturer Part Number
LFXP2-5E-5QN208C
Description
FPGA - Field Programmable Gate Array 5K LUTs 146I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LFXP2-5E-5QN208C

Number Of Macrocells
5000
Maximum Operating Frequency
200 MHz
Number Of Programmable I/os
146
Data Ram Size
10 KB
Supply Voltage (max)
1.14 V
Supply Current
17 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.26 V
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP2-5E-5QN208C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFXP2-5E-5QN208C
Manufacturer:
LATTICE
Quantity:
80
Part Number:
LFXP2-5E-5QN208C
Manufacturer:
LATTICE
Quantity:
20 000
Part Number:
LFXP2-5E-5QN208C
0
Lattice Semiconductor
LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have four
secondary clocks (SC0 to SC3) which are distributed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for
high fan-out signals.
Figure 2-11. Secondary Clock Regions XP2-40
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
I/O Bank 0
I/O Bank 5
Region 1
Region 2
Region 3
Region 4
2-13
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Region 5
I/O Bank 1
Region 6
Region 7
Region 8
I/O Bank 4
LatticeXP2 Family Data Sheet
Vertical Routing
Channel Regional
Boundary
EBR Row
Regional
Boundary
EBR Row
Regional
Boundary
DSP Row
Regional
Boundary
Architecture

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