LFXP2-5E-5QN208C Lattice, LFXP2-5E-5QN208C Datasheet - Page 24

• Manufacturer Part Number: LFXP2-5E-5QN208C
• Description: FPGA - Field Programmable Gate Array 5K LUTs 146I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5QN208C

• Number Of Macrocells: 5000
• Maximum Operating Frequency: 200 MHz
• Number Of Programmable I/os: 146
• Data Ram Size: 10 KB
• Supply Voltage (max): 1.14 V
• Supply Current: 17 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.26 V
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
MAC sysDSP Element
In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the
DSP blocks in LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available. The
overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element.
Figure 2-21. MAC sysDSP
Multiplicand
Multiplier
Signed A
Signed B
Addn
Accumsload
Serial Register B in
n
Input Data
Register B
n
n
SROB
n
Register
Register
Register
Register
Input
Input
Input
Input
m
Input Data
Register A
m
n
SROA
Serial Register A in
m
Register
Register
Register
Register
Pipeline
Pipeline
Pipeline
Pipeline
m
n
2-21
To Accumulator
To Accumulator
To Accumulator
To Accumulator
Multiplier
Register
Pipeline
x
(default)
m+n
Accumulator
CLK (CLK0,CLK1,CLK2,CLK3)
RST(RST0,RST1,RST2,RST3)
CE (CE0,CE1,CE2,CE3)
LatticeXP2 Family Data Sheet
m+n+16
(default)
Preload
(default)
m+n+16
Architecture
Output
Overflow
signal