LFXP2-5E-5QN208C Lattice, LFXP2-5E-5QN208C Datasheet - Page 32

FPGA - Field Programmable Gate Array 5K LUTs 146I/O Inst- on DSP 1.2V -5 Spd

LFXP2-5E-5QN208C

Manufacturer Part Number
LFXP2-5E-5QN208C
Description
FPGA - Field Programmable Gate Array 5K LUTs 146I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LFXP2-5E-5QN208C

Number Of Macrocells
5000
Maximum Operating Frequency
200 MHz
Number Of Programmable I/os
146
Data Ram Size
10 KB
Supply Voltage (max)
1.14 V
Supply Current
17 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.26 V
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP2-5E-5QN208C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFXP2-5E-5QN208C
Manufacturer:
LATTICE
Quantity:
80
Part Number:
LFXP2-5E-5QN208C
Manufacturer:
LATTICE
Quantity:
20 000
Part Number:
LFXP2-5E-5QN208C
0
Lattice Semiconductor
shows the diagram using this gearbox function. For more information on this topic, see TN1138,
Speed I/O
Figure 2-27. Output and Tristate Block
DQSXFER
DQSXFER
ONEG1
OPOS1
ONEG0
OPOS0
ONEG1
OPOS1
ONEG0
OPOS0
(CLKA)
(CLKB)
ECLK1
ECLK2
ECLK1
ECLK2
Interface.
CLKA
CLKB
CLK1
CLK1
TD
TD
* Shared with input register
Clock Transfer
Clock Transfer
Registers
Registers
D
D
D-Type*
D-Type*
D-Type
D-Type
D
D
Tristate Logic
Tristate Logic
Q
Q
Q
Q
*
*
D
D
Latch
Latch
Q
Q
0
1
0
1
0
1
0
1
2-29
Note: Simplified version does not show CE and SET/RESET details
0
1
0
1
0
1
0
1
D
D
D
D
D
D
D
D
/LATCH
/LATCH
/LATCH
/LATCH
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
Q
Q
Q
Q
Q
Q
Q
Q
LatticeXP2 Family Data Sheet
Comp PIO (B) in LVDS I/O Pair
True PIO (A) in LVDS I/O Pair
D
D
D
D
DDR Output
DDR Output
Latch
Latch
Latch
Latch
Registers
Registers
Q
Q
Q
Q
Output Logic
Output Logic
0
1
0
1
0
1
0
1
0
1
0
1
Programmable
Programmable
Control
Control
0
1
0
1
0
1
0
1
LatticeXP2 High
Architecture
DO
DO
TO
TO

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