A3P250-VQG100 Actel, A3P250-VQG100 Datasheet - Page 210

• Manufacturer Part Number: A3P250-VQG100
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of A3P250-VQG100

• Processor Series: A3P250
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 157
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4 - 4
Revision
v2.2
(continued)
v2.1
(May 2007)
v2.0
(April 2007)
The T
changed to T
In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input
Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz).
The "Clock Conditioning Circuit (CCC) and PLL" section was updated.
In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and
A3P600 device I/Os were updated.
Table 3-5 • Package Thermal Resistivities was updated with A3P1000
information. The note below the table is also new.
In the "Packaging Tables", Ambient was deleted.
The timing characteristics tables were updated.
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
The "PLL Macro" section was updated to include power-up information.
Table 2-11 • ProASIC3 CCC/PLL Specification was updated.
Figure 2-19 • Peak-to-Peak Jitter Definition is new.
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
The "RESET" section was updated with read and write information.
The "RESET" section was updated with read and write information.
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
PCI-X 3.3 V was added to Table 2-11 • VCCI Voltages and Compatible
Standards.
In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3
Devices was updated.
Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
The "VCCPLF PLL Supply Voltage" section was updated.
The "VPUMP Programming Supply Voltage" section was updated.
The "GL Globals" section was updated to include information about direct input
into quadrant clocks.
V
In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
Ambient was deleted from Table 3-2 • Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on
quiet I/Os)1.
JTAG
J
was deleted from the "TCK Test Clock" section.
parameter in Table 3-2 • Recommended Operating Conditions was
A
, ambient temperature, and table notes 4–6 were added.
R e vi s i o n 9
Changes
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2-64
2-40
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2-50
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N/A
3-2
3-5
3-2
3-2
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