A3P250-VQG100 Actel, A3P250-VQG100 Datasheet - Page 212

• Manufacturer Part Number: A3P250-VQG100
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of A3P250-VQG100

• Processor Series: A3P250
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 157
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4 - 6
Revision
Advance v0.6
(continued)
"Temperature Grade Offerings" was updated with the QN132.
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
The term flow-through was changed to pass-through.
Figure 2-7 • Efficient Long-Line Resources was updated.
The footnotes in Figure 2-15 • Clock Input Sources Including CLKBUF,
CLKBUF_LVDS/LVPECL, and CLKINT were updated.
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
The "WCLK and RCLK" section was updated.
The "RESET" section was updated.
The "RESET" section was updated.
The "Introduction" of the "Advanced I/Os" section was updated.
The "I/O Banks" section is new. This section explains the following types of I/Os:
Advanced
Standard+
Standard
Table 2-12 • Automotive ProASIC3 Bank Types Definition and Differences is
new. This table describes the standards listed above.
PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-
11 • VCCI Voltages and Compatible Standards
Table 2-13 • ProASIC3 I/O Features was updated.
The "Double Data Rate (DDR) Support" section was updated to include
information concerning implementation of the feature.
The "Electrostatic Discharge (ESD) Protection" section was updated to include
testing information.
Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V
Input Tolerance Capabilities in ProASIC3 Devices.
The notes in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in
ProASIC3 Devices were updated.
The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"
section is new.
A footnote was added to Table 2-14 • Maximum I/O Frequency for Single-Ended
and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum
drive strength and high slew selected).
Table 2-18 • Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications
Table 2-50 • ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type
(A3P030 device)
Table 2-51 • ProASIC3 Output Drive for Standard+ I/O Bank Type was updated.
Table 2-54 • ProASIC3 Output Drive for Advanced I/O Bank Type was updated.
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