A3P250-VQG100 Actel, A3P250-VQG100 Datasheet - Page 29

• Manufacturer Part Number: A3P250-VQG100
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of A3P250-VQG100

• Processor Series: A3P250
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 157
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User I/O Characteristics
Figure 2-2 • Timing Model
I/O Banks only)
to Advanced
(Applicable
LVPECL
(Applicable for
Advanced I/O
t
PY
Banks only)
= 0.76 ns (Advanced I/O Banks)
Clock
M-LVDS
Input LVTTL
BLVDS,
LVDS,
Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (T
VCC = 1.425 V
t
PY
(Non-Registered)
(Registered)
= 1.05 ns
t
I/O Module
I/O Module
t
t
PY
ICLKQ
ISUD
= 1.20 ns
= 0.26 ns
= 0.24 ns
D
Q
Register Cell
t
t
CLKQ
SUD
D
= 0.43 ns
= 0.55 ns
Combinational Cell
Q
(Advanced I/O Banks)
Combinational Cell
t
PD
Combinational Cell
t
PD
Clock
Input LVTTL
t
PY
= 0.87 ns
t
= 0.56 ns
PD
= 0.76 ns
= 0.47 ns
Combinational Cell
Combinational Cell
Y
Y
t
PD
t
PD
Y
= 0.47 ns
= 0.47 ns
R e v i s i o n 9
Register Cell
Combinational Cell
t
t
CLKQ
SUD
D
t
PD
Y
Y
= 0.43 ns
(Non-Registered)
= 0.55 ns
= 0.49 ns
(Advanced I/O Banks)
t
Q
I/O Module
DP
t
Clock
Input LVTTL
PY
= 2.64 ns (Advanced I/O Banks)
(Non-Registered)
(Non-Registered)
t
t
DP
I/O Module
I/O Module
DP
= 0.76 ns
Y
= 3.97 ns (Advanced I/O Banks)
= 3.66 ns (Advanced I/O Banks)
(Non-Registered)
t
I/O Module
DP
LVTTL Output drive strength = 12 mA
= 1.34 ns
t
t
D
OCLKQ
OSUD
(Registered)
I/O Module
LVTTL Output drive strength = 8 mA
LVCMOS 1.5 V Output drive strength = 4 mA
High slew rate
Q
= 0.31 ns
= 0.59 ns
t
(Advanced I/O Banks)
DP
High slew rate
= 2.64 ns
LVPECL (Applicable to
Advanced I/O Banks Only)L
J
= 70°C), Worst Case
ProASIC3 Flash Family FPGAs
High slew rate
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
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