LIS33DE STMicroelectronics, LIS33DE Datasheet - Page 17

• Manufacturer Part Number: LIS33DE
• Description: Board Mount Accelerometers MEMS MOTION SENS 3 AXIS 2G/8G SDO NANO
• Manufacturer: STMicroelectronics

Specifications of LIS33DE

• Sensing Axis: Triple
• Acceleration: 2 g, 8 g
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.16 V
• Supply Current: 0.3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Digital Output - Bus Interface: I2C, SPI
• Sensitivity: 18 mg/digit, 72 mg/digit
• Package / Case: LGA-16
• Output Type: Digital
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LIS33DE
5.1.1
I
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LIS33DE is 001110xb. SDO pad can be used to
modify less significant bit of the device address. If SDO pad is connected to voltage supply
LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’
(address 0011100b). This solution permits to connect and address two different
accelerometers to the same I
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data has
been received.
The I
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address is transmitted: the 7 LSb
represent the actual register address while the MSB enables address auto increment. If the
MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow
multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition is issued after the two sub-address bytes; if the bit is ‘0’ (Write) the
Master will transmit to the slave with direction unchanged.
Table 10.
Table 11.
Table 12.
Table 13.
2
Master
Master
Slave
Master
Slave
C operation
Slave
Master
Slave
2
C embedded inside the LIS33DE behaves like a slave device and the following
ST
ST
ST
Transfer when Master is writing one byte to slave
Transfer when Master is writing multiple bytes to slave:
Transfer when Master is receiving (reading) one byte of data from slave:
Transfer when Master is receiving (reading) one byte of data from slave
ST
SAD + W
SAD + W
SAD + W
SAD + W
SAK
SAK
2
SAK
C lines.
Doc ID 15596 Rev 1
SUB
SUB
SAK
SUB
SAK
SAK
SAK
SUB
SR
SR
SAD + R
SAD + R
DATA
SAK
SAK
SAK
SAK
DATA
DATA
DATA
DATA
Digital interfaces
SAK
NMAK
NMAK
SAK
SP
17/31
SP
SP
SP