Si8501-C-IS Silicon Laboratories Inc, Si8501-C-IS Datasheet
Si8501-C-IS
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Si8501-C-IS Summary of contents
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... Description The Si85xx products are unidirectional ac current sensors available in full-scale ranges of 5, 10, and 20 A. Si85xx products are ideal upgrades for older current- sensing technologies offering size, performance, and cost advantages over current transformers, Hall effect devices, DCR circuits, and other approaches. The Si85xx are extremely low-loss, adding less than 1.3 m ...
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Si85xx 2 Preliminary Rev. 0.21 ...
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... ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.1. Under Voltage Lockout (UVLO 2.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.3. Integrator Reset and Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4. Total Measurement Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.5. Effect of Temperature on Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6. Leading Edge Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7. FAULT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8. Safe Operating Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 ...
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... Measured from IIN to IOUT Measured from IIN to IOUT OUT, OUT1, OUT2 delay relative to input Time from VDD = UVLO HYST cal complete 4x4 mm QFN SOIC-20 1 Si8501/11/17 Si8502/12/18 Si8503/13/19 Si8501/11/17 Si8502/12/18 Si8503/13/19 Preliminary Rev. 0.21 Min Typ Max Unit 2.7 — 5.5 V — ...
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... Ambient temperature under bias Supply voltage Voltage on any pin with respect to ground (not including IIN, IOUT) Output Current Drive Lead solder temperature (10 s) Maximum Input Current Rate of Change Maximum Peak AC Input Current Limit 2 Thermal Limit (DC Current) Maximum Isolation Voltage (QFN) Maximum Isolation Voltage (SOIC-20) ...
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Si85xx Table 3. Regulatory Information CSA The Si85xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 2 VDE The Si85xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. UL The ...
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... Partial Discharge < Symbol Test Condition T S 85 IIN to IOUT = 150 ° 150 º pF, and with an input current from IIN to IOUT equal Preliminary Rev. 0.21 Si85xx Characteristic Unit SOIC-20 1414 V peak 2262 V peak 2652 1697 8000 V peak 2 9 >10 SOIC-20 Unit 150 ° ...
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Si85xx Table 8. Thermal Characteristics Parameter IC Junction-to-Air Thermal Resistance Figure 1. SOIC-20 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 8 Symbol Test Condition JA ...
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... Functional Overview The Si85xx ac current sensor family of products mimics the functionality of traditional current transformer (CT) circuits with burden resistor, diode, and output filter, but offers enhanced performance and added capabilities. These devices use inductive current sensing and on- board signal conditioning electronics to generate full-scale output signal proportional to the ac current flowing from the IIN to the IOUT terminals ...
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... R1–R4 inputs (Figure 4). UVLO in a way that resets the integrator when no current is flowing from IIN to IOUT. To achieve rated accuracy, the reset cycle must be completed prior to the start of the measurement cycle. For maximum flexibility, integrator ...
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Integrator reset Option 1 is selected by connecting T to VDD. In this mode, the Si85xx is held in reset as long as the signals on R1–R4 satisfy the logic equations of Table 11 typically used in applications ...
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... The Si85xx is a very robust current sensor. Its maximum input current rate of change is limited to 1000 A/µs. The maximum peak ac input current limit is 200 A. The thermal limit or continuous dc current flow limit Exceeding these limits may cause long-term reliability issues. Refer to “AN329: Extending the Full-Scale Range of the Si85xx” ...
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... Application Information 3.1. Board Layout The Si85xx is connected in the series path of the current to be measured. The Si85xx must be located as far as possible from transformer and other magnetic field sources. Like other analog components, the Si85xx should be powered from a low-noise dc source and, preferably low-noise analog ground plane. ...
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... Ping-Pong mode is recommended for full-bridge applications over 2-wire because it uses all four inputs, making the reset function tolerant to single-point signal failures. In 4-Wire Ping-Pong mode, current appears on OUT2 when R1 is high and R2 is low, and appears on OUT1 when R3 is high and R4 is low as shown in the full-bridge timing example of Figure 12 ...
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... This reset must be synchronized with the system switch timing signals to ensure that current is measured during the appropriate time; so, the Si85xx integrator reset circuitry uses system timing as its reference. Timing signals connect to reset inputs R1 ...
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Si85xx Table 11. Si85xx Output and Reset Mode Summary Output Mode MODE R4 Single-Ended 1 0 2-Wire Ping Pong 4-Wire Ping Pong 0 1 *Note: Device is in reset when Reset State = ...
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... As explained in Section “2.3. Integrator Reset and Current Measurement”, the signals applied to R1–R4 can control integrator reset in real time (Option 1), or they can trigger a reset event of programmable duration (Option 2). Referring to Figure 13, reset timing is exclusively a function of the signals applied to R1–R4 when TRST is tied to VDD ...
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... Table high (transition to the TRUE state). Because this timer is re-triggerable, R1–R4 must remain TRUE for the duration of the desired t Figure 14. Should R1–R4 transition FALSE during t measurement accuracy due to higher integrator offset error. CURRENT R1–R4 STATE Si85xx STATUS Si85xx OUTPUT Figure 14 ...
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Measurement Watchdog Timer and FAULT Output A built-in watchdog timer disables measurement and holds OUT or OUT1 and OUT2 at their minimum values when the time between integrator resets exceeds the FAULT Detect Time. The output signal from this ...
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... A peak current applied, then the output voltage (OUT) will (assuming VDD = 5 V peak current is applied, then the output returns to the nominal 2 V output. The head room of OUT is VDD–1.4 V. Figure 16 illustrates the head room limitation of the Si85xx versus supply. ...
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... TRST In this example, the current measurement is made when the buck switch is on; so, PH2 is chosen as the reset signal by connecting PH2 to R1 and grounding R2 and R3. The PH2 signal can be obtained at the input of the driver external to the PWM controller or the output of the controller's internal driver (through a resistor divider if the driver output swings beyond the device VDD range) ...
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... TRST to VDD. As shown in the timing diagram of Figure 18, integrator reset occurs when current circulates between Q1 and Q2 and between Q3 and Q4 (i.e. when current is not being sourced from VIN). The external driver delay ensures reset is complete prior to the start of measurement. ...
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Push-Pull Converter Example The Push-Pull converter of Figure 19 uses 2-Wire Ping Pong output mode. As shown in the timing diagram, the integrator reset occurs when the inputs of both the PH1 and PH2 drivers are low. As shown, ...
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... Output in single-ended output mode, or one of two outputs in Ping-Pong mode. OUT2 Second of two Ping-Pong mode outputs TRST Reset time control GND Ground IOUT Current output terminal IIN Current input terminal VDD Power supply input MODE Mode control input Preliminary Rev. 0.21 IIN Si851x IOUT Description ...
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... Output in single-ended output mode, or one of two outputs in Ping-Pong mode. OUT2 Second of two Ping-Pong mode outputs TRST Reset time control GND Ground IOUT Current output terminal IIN Current input terminal Preliminary Rev. 0.21 Si85xx 20-Pin SOIC IIN IIN IIN IIN Si851x IIN IOUT ...
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... Si85xx 6. Ordering Guide New Full Scale Initial Current Accuracy OPNs ( Si8501-C-IM 5 Si8502-C-IM 10 Si8503-C-IM 20 Si8501-C-IS 5 Si8502-C-IS 10 Si8503-C-IS 20 Si8511-C-IM 5 Si8512-C-IM 10 Si8513-C- Si8511-C-IS 5 Si8512-C-IS 10 Si8513-C-IS 20 Si8517-C-IM 5 Si8518-C-IM 10 Si8519-C-IM 20 Si8517-C-IS 5 Si8518-C-IS 10 Si8519-C-IS 20 Notes: 1. See "2.4. Total Measurement Error" on page 11 for more information. 2. All packages are RoHS-compliant. Moisture Sensitivity level is MSL3 with peak reflow temperature of 260 °C according to the JEDEC industry classification, and peak solder temperature. 3. Since the initial accuracy for all devices is now specified as ± ...
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Package Outline—12-Pin QFN Figure 22 illustrates the package details for the Si85xx. Table 14 lists the values for the dimensions shown in the illustration. Figure 22. 12-Pin QFN Package Diagram Table 14. QFN-12 Package Diagram Dimensions Dimension A A1 ...
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Si85xx 8. Recommended PCB Landing Pattern (12-Pin QFN) Figure 23 illustrates the PCB land pattern details for the 12-pin QFN package. Table 15 lists the values for the dimensions shown in the illustration. Figure 23. 12-Pin QFN PCB Land Pattern ...
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Top Marking (QFN) Line 1 Marking: Device Part Number Line 2 Marking: TTTTTT = Mfg Code Line 3 Marking: Circle Bottom-Left Justified YY = Year WW = Work Week Si85XX TTTTTT YYWW Figure 24. QFN Top Marking Table 16. ...
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Si85xx 10. Package Outline: Wide Body SOIC Figure 25 illustrates the package details for the wide-body SOIC package. Table 17 lists the values for the dimensions shown in the illustration. 30 Figure 25. 20-Pin Wide Body SOIC Preliminary Rev. 0.21 ...
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Table 17. 20-Pin Wide Body SOIC Package Diagram Dimensions Dimension θ aaa bbb ccc ddd eee fff Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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Si85xx 11. Recommended PCB Landing Pattern (20-Pin SOIC) Figure 26 illustrates the PCB land pattern details for the 20-pin SOIC package. Table 18 lists the values for the dimensions shown in the illustration. Figure 26. 20-Pin SOIC PCB Land Pattern ...
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Top Marking (SOIC) Line 1 Marking: Device Part Number Line 2 Marking Year WW = Work Week TTTTTT = Mfg Code Line 3 Marking: Circle = 1.5 mm Diameter (Center Justified) Country of Origin ISO Code Abbreviation ...
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Si85xx OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Updated Table 1, “Electrical Specifications,” on page 4. Added 20-pin wide-body SOIC package option. Updated "6. Ordering Guide" on page 26. All devices are now ...
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N : OTES Preliminary Rev. 0.21 Si85xx 35 ...
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