L3G4200D STMicroelectronics, L3G4200D Datasheet
L3G4200D
Specifications of L3G4200D
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L3G4200D Summary of contents
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... The L3G4200D has a full scale of ±250/±500/ ±2000 dps and is capable of measuring rates with a user-selectable bandwidth. The L3G4200D is available in a plastic land grid array (LGA) package and can operate within a temperature range of -40 °C to +85 °C. Package -40 to +85 LGA-16 (4x4x1 ...
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... I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.1 5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/29 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 17116 Rev L3G4200D ...
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... L3G4200D 5.2.1 5.2.2 5.2.3 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Doc ID 17116 Rev 2 Contents 3/29 ...
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... Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 16. Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 22 Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 22 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4/29 Doc ID 17116 Rev 2 L3G4200D ...
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... L3G4200D List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. L3G4200D external low-pass filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. ...
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... FIFO CIRCUITS PHASE GENERATOR +Ω Ω Y RES RES RES +Ω RES X Doc ID 17116 Rev I2C SCL/SPC SDA/SDO/SDI E SPI C T SDO CLOCK CONTROL LOGIC & & INTERRUPT GEN Vdd_IO 12 1 BOTTOM SCL/SPC VIEW SDA/SDI/SDO 9 4 SDO/SA0 8 5 L3G4200D INT1 DRDY/INT2 AM07225v1 AM07226v1 ...
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... Figure 3. L3G4200D external low-pass filter values a. Pin 14 PLLFILT maximum voltage level is equal to Vdd. Name Vdd_IO Power supply for I/O pins 2 SCL I C serial clock (SCL) SPC SPI serial port clock (SPC) 2 SDA I C serial data (SDA) SDI SPI serial data input (SDI) ...
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... Block diagram and pin description Table 3. Filter values 8/29 Parameter Doc ID 17116 Rev 2 L3G4200D Typical value 10 nF 470 nF 10 kΩ ...
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... L3G4200D 2 Mechanical and electrical characteristics 2.1 Mechanical characteristics Table 4. Mechanical characteristics @ Vdd = 3 °C, unless otherwise noted Symbol Parameter FS Measurement range So Sensitivity Sensitivity change vs. SoDr temperature DVoff Digital zero-rate level Zero-rate level change OffDr (3) vs. temperature (4) NL Non linearity DST Self-test output change ...
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... Operating temperature Top range 1. The product is factory calibrated at 3 Typical specifications are not guaranteed. 10/29 Test condition (3) Selectable by digital interface Selectable by digital interface Test condition Doc ID 17116 Rev 2 L3G4200D (1) (2) Min. Typ. Max. 2.4 3.0 3.6 1.71 Vdd+0.1 6.1 1.5 5 -40 ...
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... L3G4200D 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 7. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) CS hold time tsu(SI) SDI input setup time ...
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... Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. 12/ standard mode Min Max 0 100 4.7 4.0 250 0 3.45 1000 300 4 4.7 4 4.7 (c) Doc ID 17116 Rev 2 L3G4200D 2 ( fast mode Unit Min Max 0 400 kHz 1.3 µs 0.6 100 ns 0 0.9 µs ( 0.1C 300 b ...
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... L3G4200D 2.5 Absolute maximum ratings Any stress above that listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...
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... The LGA package is compliant with the ECOPACK It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/. 14/29 ® , RoHS and “Green” standard. Doc ID 17116 Rev 2 L3G4200D ...
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... FIFO The L3G4200D embeds a 32-slot, 16-bit data FIFO for each of the three output channels: yaw, pitch, and roll. This allows consistent power saving for the system, as the host processor does not need to continuously poll data from the sensor. Instead, it can wake up only when needed and burst the significant data out from the FIFO ...
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... In stream mode, data from yaw, pitch, and roll measurements are stored in the FIFO. A watermark interrupt can be enabled and set as in FIFO mode. The FIFO continues filling until full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the FIFO discards the 16/29 Figure 8. Doc ID 17116 Rev 2 L3G4200D ...
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... L3G4200D older data as the new data arrives. Programmable watermark level events can be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3). Stream mode is represented in Figure 9. Stream mode 3.2.4 Bypass-to-stream mode In bypass-to-stream mode, the FIFO starts operating in bypass mode, and once a trigger ...
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... OUT_X, OUT_Y and OUT_Z registers and both single read and read_burst (X,Y & Z with auto-incremental address) operations can be used. In read_burst mode, when data included in OUT_Z_H is read, the system again starts to read information from addr OUT_X_L. 18/29 Figure 11). Doc ID 17116 Rev 2 L3G4200D ...
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... Vdd and common ground, 100 nF between Vdd_IO and common ground) should be placed as near as possible to the device (common design practice). The L3G4200D IC includes a PLL (phase locked loop) circuit to synchronize driving and sensing interfaces. Capacitors and resistors must be added at the PLLFILT pin (as shown in Figure 12) to implement a second-order low-pass filter ...
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... Digital interfaces 5 Digital interfaces The registers embedded in the L3G4200DH may be accessed through both the I serial interfaces. The latter may be software-configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pins. To select/exploit the I CS line must be tied high (i.e., connected to Vdd_IO). ...
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... If they match, the device considers itself addressed by the master. The slave address (SAD) associated with the L3G4200DH is 110100xb. The SDO pin can be used to modify the least significant bit (LSb) of the device address. If the SDO pin is connected to the voltage supply, LSb is ‘1’ (address 1101001b). Otherwise, if the SDO pin is connected to ground, the LSb value is ‘ ...
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... CS, SPC, SDI, and SDO. 22/29 SAD + W SUB SAK SAK SUB SR SAK SAK SR SAD+R SAK SAK DATA Doc ID 17116 Rev 2 L3G4200D DATA DATA SAK SAK SAD + R NMAK SAK DATA MAK MAK NMAK DATA DATA ...
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... L3G4200D Figure 13. Read and write protocol CS SPC SDI SDO CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. SPC is the serial port clock and is controlled by the SPI master stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output ...
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... AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 Doc ID 17116 Rev 2 L3G4200D DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 ...
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... L3G4200D Figure 17. Multiple byte SPI write protocol (2-byte example) CS SPC SDI RW MS 5.2.3 SPI read in 3-wire mode 3-wire mode is entered by setting the SIM (SPI serial interface mode selection) bit CTRL_REG2. Figure 18. SPI read protocol in 3-wire mode CS SPC SDI/O The SPI read command is performed with 16 clock pulses: Bit 0: READ bit. The value is 1. Bit 1: MS bit. When 0, do not increment address ...
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... Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK trademark. 26/29 Doc ID 17116 Rev 2 L3G4200D ® ...
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... L3G4200D Figure 19. LGA-16: mechanical data and package dimensions Doc ID 17116 Rev 2 Package information 27/29 ...
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... Revision history 7 Revision history Table 18. Document revision history Date 01-Apr-2010 03-Sep-2010 28/29 Revision 1 Initial release. 2 Complete datasheet review. Doc ID 17116 Rev 2 L3G4200D Changes ...
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... L3G4200D Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...